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研究生:張瑋仁
研究生(外文):Wei-Jen Chang
論文名稱:低電壓互補式金氧半製程下可相容高工作電壓之靜電放電防護設計
論文名稱(外文):High-Voltage-Tolerant ESD Protection Design in Low-Voltage CMOS Processes
指導教授:柯明道柯明道引用關係
指導教授(外文):Ming-Dou Ker
學位類別:博士
校院名稱:國立交通大學
系所名稱:電子工程系所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2007
畢業學年度:96
語文別:英文
論文頁數:134
中文關鍵詞:靜電放電二次崩潰電流混合電壓輸入輸出界面低電壓驅動雙載子接面電晶體可耐高工作電壓之靜電放電箝制電路真空螢光顯示器高壓P型矽控整流器人體放電模式機械放電模式
外文關鍵詞:electrostatic dischargesecondary breakdown currentmixed-voltage I/O interfaceslow-voltage-triggered PNPhigh-voltage-tolerant ESD clamp circuitvacuum-fluorescent-displayhigh-voltage P-type silicon controlled rectifierhuman-body-modelmachine-model
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隨著半導體製程的進步與發展,積體電路產品已經成為民生用品般地大量製造與使用,許多整合多功能的系統晶片(SoC)已經成為各電子公司的產品研發主力,電子產業也在這個領域有長足的進步與發展。但由於半導體製造技術的日新月異,使得積體電路對靜電放電防護的能力下降很多,同時由於操作電壓一直在下降,但是週邊電路的電壓卻未隨半導體製程的進步而降低,所以在扮演晶片輸入輸出媒介的混合電壓界面(Mixed-Voltage I/O Interface)上將會產生許多問題,尤其在電子系統訊號整合上。因此要在此混合電壓電路加上其靜電放電保護電路,需要考量界面電壓轉換、混合電壓界面間的漏電流 (Leakage Current)、混合電壓界面電路的可靠度(Reliability)等問題。因此,在混合電壓界面上,如何仔細評估這些問題進而設計出具有高的靜電放電防護能力的電路將是當今以及未來積體電路設計上的重要課題,這個主題隨著半導體製程進入 0.13微米 以及90奈米之後,對積體電路設計產業更加重要。另外,隨著高壓金氧半製程在面版驅動電路(LCD Driver ICs)、電源供應器(Power Supplies)、電源管理(Power Management),以及汽車電子(Automotive Electronics)等使用的普及化,對於使用在這些應用的輸出端以及當作靜電放電保護元件的高壓電晶體來說,靜電放電的可靠度問題將比在一般低壓製程的元件來得嚴重,因此如何有效改善靜電放電耐壓能力,將是這些高壓積體電路設計上很重要的課題,這個主題也隨著這些產業應用上的多元化而更趨重要。所以本論文分別針對了混合電壓界面電路以及高壓金氧半製程應用上的限制與困難作討論,並進一步設計出有效的靜電放電防護電路以適用在各相關應用之積體電路晶片。
首先,本論文提出了一種新型的低電壓驅動雙載子接面電晶體(Low-Voltage-Triggered PNP, LVTPNP)來當作混合電壓輸入輸出界面(Mixed-Voltage I/O Interfaces)之靜電放電保護元件。此新型靜電放電保護元件是在CMOS製程中寄生的雙載子接面電晶體的N型井(N-Well)以及P型基板(P-Substrate)接面上,額外植入N型或是P型的擴散離子所構成,以降低N型井以及P型基板接面的崩潰電壓,當輸入電壓比VDD高(Over-VDD)或比VSS低(Under-VSS)時,不會有漏電以及閘極氧化層的可靠度問題。在0.35微米互補式金氧半製程,已經驗證了此低電壓驅動雙載子接面電晶體會比傳統寄生的雙載子接面電晶體的靜電放電耐受程度來得高,而該元件的最佳化佈局方式(Layout Style)也在0.35微米以及0.25微米互補式金氧半製程中驗證來提升元件本身的靜電放電耐受程度,經由實驗證明,具有多指狀(Multi-Finger)佈局方式的元件靜電放電耐受程度會比單指狀(Single Finger)的要來得高。除此之外,在0.25微米製程的晶片驗證下,具有多指狀佈局方式的低電壓驅動雙載子接面電晶體搭配電源間的靜電放電箝制電路(Power-Rail ESD Clamp Circuit)成功地提升了非同步數位用戶專線(Asymmetric Digital Subscriber Line, ADSL)輸入級的靜電放電耐受程度,此輸入級的訊號界於5V到-1V之間,此電壓同時超過了該IC之VDD(2.5V)和低過了該IC之VSS(0V)。
本論文研究的第二部分,為了提供有效的靜電放電防護於1.2/2.5V混合電壓輸入輸出界面,本論文提出了新型的靜電放電保護架構並在0.13微米製程中成功驗證,此架構同時利用了靜電放電匯流排(ESD BUS)以及可耐高工作電壓之靜電放電箝制電路(High-Voltage-Tolerant ESD Clamp Circuit)來實現。當混合電壓輸入輸出界面的銲墊(Pad)對VDD(或VSS)之間遭受靜電轟擊或是輸入輸出腳對腳(Pin-to-Pin)之間遭受靜電轟擊時,此靜電放電保護架構都可以提供相對應的放電路徑來避免內部電路遭受靜電損壞。在此靜電放電防護電路中,可耐高工作電壓之靜電放電箝制電路都是利用1.2V低壓元件來實現,並可安全地在2.5V的電壓偏壓下工作而不會有閘極氧化層的可靠度問題。由實驗可知,比起一般的堆疊式電晶體(Stacked-NMOS)而言,基板觸發(Substrate Triggered)技術可以有效提升該可耐高工作電壓之靜電放電箝制電路的導通速度以及靜電放電耐受程度。在堆疊式電晶體的元件尺寸為480um/0.2um的大小之下,1.2/2.5V的混合電壓輸入輸出界面之人體放電模式靜電放電耐壓能力(HBM ESD levels)可以從原本的5kV增加到6.5kV;同時,機械放電模式靜電放電耐壓能力(MM ESD levels)可以從原本的275V增加到400V。
本論文研究的第三部份,為了提升應用在車用電子(Automotive Electronics)中的真空螢光顯示器(Vacuum-Fluorescent-Display, VFD)驅動IC的靜電放電耐受程度,本論文提出一種新型的靜電放電保護的元件結構。此元件結構是在高壓P型的金氧半電晶體(HVPMOS)的汲極當中植入一個N型離子佈植來形成一個嵌入式高壓P型矽控整流器(High-Voltage P-Type Silicon Controlled Rectifier, HVPSCR)路徑,此結構只需要加入額外的N型離子局部佈局面積即可實現。在0.5微米的互補式金氧半製程中,成功驗證了具有此嵌入式高壓P型矽控整流器的真空螢光顯示器驅動積體電路的人體放電模式靜電放電耐壓能力可以從不到500V增加到8kV;同時,當元件尺寸為500um/2um、600um/2um以及800um/2um時,機械放電模式之靜電放電耐壓能力可以通過1100V、1300V以及1900V的靜電測試。此外,此嵌入式高壓P型矽控整流器的真空螢光顯示器驅動積體電路可成功通過 �b200mA的閂鎖(Latchup)測試。
本論文研究的第四部分,觀察到使用在輸出端以及當作靜電放電保護元件的高壓電晶體,靜電放電的可靠度問題比在一般製程的元件來得嚴重,因此本論文利用40-V金氧半製程對於不同元件結構以及汲極到閘極的距離(Layout Spacing from Drain to Polygate)做一深入探討。實驗結果成功驗證了汲極下端沒有植入的飄移摻雜(Drift Implant)佈局的高壓金氧半電晶體比起汲極下端有加入移摻雜的高壓金氧半電晶體有較高的二次崩潰電流(Secondary Breakdown Current, It2)以及較好的靜電放電防護能力。在所有元件結構當中,嵌入在高壓N型的金氧半電晶體中的高壓N型矽控整流器(HVNSCR)並在汲極下端移除了飄移摻雜的結構,具有最高的二次崩潰電流以及靜電放電耐受度。此外,元件模擬技巧也成功地分析了有無飄移摻雜對於元件內電流分佈的影響。
本論文分別針對了混合電壓界面電路以及高壓金氧半製程應用上的限制與困難作討論,並進一步設計出有效的靜電放電防護電路應用在各相關之積體電路晶片。本博士論文所提出電路已經有相對應的國際期刊與會議論文發表以及專利申請。
The scaling trend of the CMOS technology is toward the nanometer region to increase the speed and density of the transistors in integrated circuits. Due to the reliability issue, the power supply voltage is also decreased with the advanced technologies. However, in an electronic system, some circuits could be still operated at high voltage levels. If the circuits realized with low-voltage devices are operated at high voltage levels, the gate-oxide breakdown and leakage issues will occur. Therefore, for the CMOS integrated circuits (ICs) with the mixed-voltage I/O interfaces, the on-chip electrostatic discharge (ESD) protection circuits will meet more design constraints and difficulties. The on-chip ESD protection circuit for mixed-voltage I/O interfaces should meet the gate-oxide reliability constraints and prevent the undesired leakage current paths during normal circuit operating operation. During ESD stress condition, the on-chip ESD protection circuit should provide effective ESD protection for the internal circuits. In high-voltage CMOS technology, high-voltage transistors have been widely used for display driver ICs, power supplies, power management, and automotive electronics. The high-voltage MOSFET was often used as the ESD protection device in the high-voltage CMOS ICs, because it can work as both of output driver and ESD protection device simultaneously. With an ultra-high operating voltage, the ESD robustness of high-voltage MOSFET is quite weaker than that of low-voltage MOSFET. Hence, how to improve the ESD robustness of HV NMOS with a reasonable silicon area is indeed an important reliability issue in HV CMOS technology. In this thesis, some new ESD protection structures are proposed to improve ESD robustness of the high-voltage IC products fabricated in CMOS technology.
To protect the mixed-voltage I/O interfaces for signals with voltage levels higher than VDD (over-VDD) and lower than VSS (under-VSS), ESD protection design with the low-voltage-triggered PNP (LVTPNP) device in CMOS technology is proposed. The LVTPNP is realized by inserting N+ or P+ diffusion across the junction between N-well and P-substrate of the PNP device. The LVTPNP devices with different structures have been investigated and compared in CMOS processes. The experimental results in a 0.35-um CMOS process have proven that the ESD level of the proposed LVTPNP is higher than that of the traditional PNP device. Furthermore, layout on LVTPNP device for ESD protection in mixed-voltage I/O interfaces is also optimized in this work. The experimental results verified in both 0.35-um and 0.25-um CMOS processes have proven that the ESD levels of the LVTPNP drawn in the multi-finger layout style are higher than that drawn in the single finger layout style. Moreover, one of the LVTPNP devices drawn with the multi-finger layout style has been used to successfully protect the input stage of an ADSL IC in a 0.25-um salicided CMOS process.
To increase the system-on-chip ESD immunity of micro-electronic products against system-level ESD stress, the chip-level ESD/EMC protection design should be enhanced. Considering gate-oxide reliability, a new ESD protection scheme with ESD_BUS and high-voltage-tolerant ESD clamp circuit for 1.2/2.5 V mixed-voltage I/O interfaces is proposed in this chapter. The devices used in the high-voltage-tolerant ESD clamp circuit are all 1.2 V low-voltage NMOS/PMOS devices which can be safely operated under the 2.5 V bias conditions without suffering from the gate-oxide reliability issue. The four-mode (PS, NS, PD, and ND) ESD stresses on the mixed-voltage I/O pad and pin-to-pin ESD stresses can be effectively discharged by the proposed ESD protection scheme. The experimental results verified in a 0.13 um CMOS process have confirmed that the proposed new ESD protection scheme has high human-body-model (HBM) and machine-model (MM) ESD robustness with a fast turn-on speed. The proposed new ESD protection scheme, which is designed with only low-voltage devices, is an excellent and cost-efficient solution to protect mixed-voltage I/O interfaces.
To greatly improve ESD robustness of the vacuum-fluorescent-display (VFD) driver IC for automotive electronics applications, a new electrostatic discharge protection structure of high-voltage P-type silicon controlled rectifier (HVPSCR) embedded into the high-voltage PMOS device is proposed. By only adding the additional N+ diffusion into the drain region of high-voltage PMOS, the TLP-measured secondary breakdown current (It2) of output driver has been greatly improved greater than 6A in a 0.5-µm high-voltage CMOS process. Such ESD-enhanced VFD driver IC, which can sustain HBM ESD stress of up to 8kV, has been in mass production for automotive applications in car without latchup problem. Moreover, with device widths of 500um, 600um, and 800um, the MM ESD levels of the HVPSCR are as high as 1100V, 1300V, and 1900V, respectively.
The dependences of drift implant and layout parameters on ESD robustness in a 40-V CMOS process have been investigated in silicon chips. From the experimental results, the HV MOSFETs without drift implant in the drain region have better TLP-measured It2 and ESD robustness than those with drift implant in the drain region. Furthermore, the It2 and ESD level of HV MOSFETs can be increased as the layout spacing from the drain diffusion to polygate is increased. It was also demonstrated that a specific test structure of HV n-type silicon controlled rectifier (HVNSCR) embedded into HV NMOS without N-drift implant in the drain region has the excellent TLP-measured It2 and ESD robustness. Moreover, due to the different current distributions in HV NMOS and HVNSCR, the dependences of the TLP-measured It2 and HBM ESD levels on the spacing from the drain diffusion to polygate are different.
In this thesis, the novel ESD protection circuits have been developed for mixed-voltage
I/O interfaces and high-voltage CMOS process with high ESD robustness. Each of the ESD protection circuits has been successfully verified in the testchips.
ABSTRACT (CHINESE) i
ABSTRACT (ENGLISH) v
ACKNOWLEDGEMENTS viii
CONTENTS ix
TABLE CAPTIONS xiii
FIGURE CAPTIONS xiv

CHAPTER 1 INTRODUCTION 1
1.1 Background 1
1.2 Issue of Mixed-Voltage I/O Interfaces 1
1.3 Issue of High-Voltage CMOS ICs 4
1.4 Thesis Organization 5
Figures 7

CHAPTER 2 OVERVIEW ON ESD PROTECTION DESIGN FOR MIXED-VOLTAGE I/O CIRCUITS 11
2.1 Substrate-Triggered Stacked-NMOS Device 11
2.2 Extra ESD Device between I/O Pad and VSS 13
2.3 Extra ESD Device between I/O Pad and VDD 15
2.4 ESD Protection Design with ESD Bus 16
2.5 Special Applications 17
2.6 Summary 18
Figures 19

CHAPTER 3 ESD PROTECTION DESIGN WITH LOW-VOLTAGE-TRIGGERED PNP (LVTPNP) DEVICES FOR MIXED-VOLTAGE I/O INTERFACE
25
3.1 ESD Protection Design with LVTPNP Device 25
3.1.1 Device Structures and TLP-Measured I-V Characteristics 26
3.1.2 Layout Parameters of LVTPNP Devices on HBM ESD Levels 27
3.1.3 Multi-Finger Layout Style for LVTPNP 29
3.2 Application in ADSL Interface 31
3.2.1 ESD Protection Design with LVTPNP for Input Stage of ADSL 31
3.2.2 HBM ESD Levels of ADSL with the Type3 LVTPNP 33
3.2.3 Failure Analysis 34
3.3 Summary 34
Tables 36
Figures 40

CHAPTER 4 HIGH-VOLTAGE-TOLERANT ESD CLAMP CIRCUIT IN LOW-VOLTAGE THIN-OXIDE TECHNOLOGY 55
4.1 ESD Protection Scheme for Mixed-Voltage I/O Interface 55
4.2 High-Voltage-Tolerant ESD Clamp Circuit 57
4.2.1 Substrate-Triggered STNMOS 57
4.2.2 Operation Principle 58
4.2.3 H-Spice Simulated Results 59
4.3 Experiment Results 60
4.3.1 Characteristics of Substrate-Triggered STNMOS 60
4.3.2 Turn-on Speed 61
4.3.3 ESD Robustness of STNMOS Devices 62
4.4 Summary 62
Tables 63
Figures 64



CHAPTER 5 ESD PROTECTION DESIGN FOR AUTOMOTIVE VACUUM-FLUORESCENT-DISPLAY (VFD) DRIVER IC 72
5.1 Original Design for VFD I/O 72
5.1.1 Device Structure and I-V Characteristic of the HVPMOS 73
5.1.2 ESD robustness and Failure Analysis 73
5.2 New ESD Design for VFD I/O 74
5.2.1 Device Structure and Turn-on Mechanism of the HVPSCR 74
5.2.2 ESD Protection Design for VFD I/O with Both HVPSCR and
Power-Rail ESD Clamp Circuit 76
5.3 Experimental Results 77
5.3.1 I-V Characteristic of the HVPSCR 77
5.3.2 ESD robustness of the VFD Driver IC 79
5.4 Summary 79
Tables 81
Figures 82

CHAPTER 6 ESD ROBUSTNESS OF ON-CHIP ESD PROTECTION DEVICES IN 40-V CMOS TECHNOLOGY 96
6.1 Device Structures in 40-V CMOS Process 96
6.1.1 HV NMOS With or Without N-Drift Implant 97
6.1.2 HV PMOS With or Without P-Drift Implant 97
6.1.3 HVNSCR With or Without N-Drift Implant 98
6.2 Experimental Results and Discussion 99
6.2.1 TLP-Measured I-V Characteristics 99
6.2.2 HBM ESD Robustness 103
6.2.3 Failure Analysis 105
6.3 Summary 105
Tables 106
Figures 107

CHAPTER 7 CONCLUSIONS AND FUTURE WORK 120
7.1 Main Results of This Thesis 120
7.2 Future Works 122

REFERNCES 123
VITA 131
PUBLICATION LIST 132
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