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研究生:林俊誼 
研究生(外文):Jyun-Yi Lin
論文名稱:90奈米混合臨界電壓標準元件庫
論文名稱(外文):90nm Mixed-Threshold Voltage Standard Cell Library Design and Characterization
指導教授:周世傑周世傑引用關係
指導教授(外文):Shyh-Jye Jou
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子工程系所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2007
畢業學年度:96
語文別:英文
論文頁數:74
中文關鍵詞:90奈米混合臨界電壓標準元件庫
外文關鍵詞:90nm Mixed-Threshold Voltage Standard Cell Library Design and Characterization
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隨著製程的進步以及各種攜帶型電子產品需求的增加,功率消耗對於這些產品變得相當的重要,例如:使用太陽能電池的助聽器 、新型手機…等。在本篇論文中,我們提出首先介紹關於深次微米CMOS標準元件庫的時脈效能和能量特性化流程的概論。接著我們提出一種在電路中使用混合臨界電壓電晶體的方式來取代單一臨界電壓電晶體的方式,使電路能夠在不犧牲速度的情況下,達到低功率的效果。我們找出在拉升及拉降結構中延遲時間的關鍵路徑,以及關鍵路徑中最長延遲時間的關鍵電晶體。接著我們將關鍵電晶體置換成較低臨界電壓的電晶體,並且重新調整較低臨界電壓的電晶體尺寸,使新電路的速度能與原本的電路接近。利用這種方式,我們不需要增加額外的電路,也不需要更改電路架構,即可達到低功率的需求。此外大部分電晶體路徑中的漏電流將會被阻擋住。
我們利用這種混合臨界電壓的方式來建立90奈米低功率標準元件庫。接著利用這個低功率標準元件庫來合成電路並且和高臨界電壓標準元件庫的效能比較。我們的混合臨界電壓標準元件庫在動態功率消耗上可以節省5%到30%,在延遲時間功率乘積上可以節省20%到55%,而在面積方面因為佈局規則的限制,增加了0%到40%。
With the advance of process technology and the increasing requirement of portable electric products, the power consumption of these products becomes very important. In this thesis, we first make the overview about the advanced characterization flow of timing and power in deep submicron CMOS standard cell library. Then, we propose a methodology using mixed-threshold voltage transistors in a circuit instead of single normal-threshold voltage transistors to reduce power consumption with the same timing performance. We find out the critical path and the critical transistors on the critical path that result in the longest delay time in the pull-up and pull-down networks, respectively. Then we replace the critical transistors with lower threshold voltage transistors and do resizing to meet the time performance of original circuits. Using this technique, we do not have to use additional transistors and do not change the structure of circuits to obtain the requirement of low power. Moreover, the leakage current is also blocked in most of the transistor paths.
We apply this mixed-threshold voltage methodology to establish our 90nm low power standard cell library. Then we use many design examples to compare the performance with the high-Vt standard cell library and make the conclusion that we can have around 5% to 30% dynamic power saving, 20% to 55% delay-power product saving and the area is 0% to 40% larger than the standard cells with single high-Vt transistors.
Contents
Chapter 1 Introduction 1
1.1 Introduction of Standard Cell Library 1
1.2 Deep-submicron Circuit Design Issues 2
1.3 Motivation and Goals 3
1.4 Thesis Organization 4
Chapter 2 Background Overview 6
2.1 Power Dissipation in CMOS circuits 6
2.1.1 Dynamic Power Dissipation 6
2.1.2 Static Power Dissipation 7
2.2 Common Formats of Standard Cell Library 10
2.3 Brief Introduction to Liberty File 11
2.3.1 Classification of Power [4] [5] 14
2.3.2 Classification of Time 18
2.3.3 Create Look-up Table 20
2.4 Design of Standard Cell Library 22
2.5 Summary 23
Chapter 3 Timing and Power Model Characterization Flow 24
3.1 Timing Characterization Flow 24
3.1.1 Transition Time and Propagation Delay time 24
3.1.2 Input Capacitance 28
3.2 Power Characterization Flow 29
3.2.1 Internal Power 29
3.2.2 Leakage Power 30
3.3 Summary 31
Chapter 4 Low Power Standard Cell Library 32
4.1 Overview of Low Power Standard Cell Design Methodology 32
4.1.1 Multiple Threshold Voltage Circuit 33
4.1.2 Multiple Supply Voltage 40
4.2 Standard Cell Selection Rule 42
4.3 Low Power Standard Cell Library Design Flow 45
4.4 Cell Design 52
4.4.1 INV 57
4.4.2 3-input NAND and AOI31 58
4.4.3 1-bit Half Adder 61
4.4.4 DFF and SETDFF 62
4.5 Summary 65
Chapter 5 Design Examples by Low Power Standard Cell Library 66
5.1 C17 66
5.2 32 bit Ripple Adder 67
5.3 32-bit Wallace Tree Multiplier 68
5.4 32-bit Shift Register 70
Chapter 6 Conclusions 72
Reference 73
[1] L. Wei, K. Roy, and V. De, “Low Voltage Low Power CMOS Design Techniques for Deep Submicron ICs,” VLSI Design, 2000. Thirteenth International Conference on 3-7 Jan. 2000, pp: 24-29.
[2] K.S. Yeo and K. Roy, Low-Voltage, Low-Power VLSI Subsystems, 1st ed. New York: McGraw-Hill, 2005.
[3] IEEE Standard for an Advanced Library Format (ALF) Describing Integrated Circuit (IC) Technology, Cells, and Blocks, IEEE Standard 1603TM-2003, 2004.
[4] Synopsys Corporation, Library Compiler User Guide: Modeling Timing and Power, 2004.
[5]郭建興, 標準元件庫特徵化程式使用者手冊 (User’s Guide of Characterization Utilities), 2003.
[6] Neil H. E. Weste, and David Harris, CMOS VLSI DESIGN – A Circuit and System Perspective,” 3rd ed., Addison Wesley, 2004.
[7] S. Mutoh, et al., “1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS”, IEEE Journal of Solid-State Circuits, vol.30, no.8, pp. 847-854, 1995.
[8] S. Shigematsu, S. Mutoh, Y. Matsuya, Y. Tanabe, J. Yamada, “A 1-V high speed MTCMOS circuit scheme for power-down applications”, IEEE J. Solid-State Circuits, vol.32, pp. 861-869, Nov. 6, 1997.
[9] H. Kawaguchi, K. Nose and T. Sakurai, “A CMOS Scheme for 0.5V Supply Voltage with Pico-Ampere Standby Current”, IEEE International Solid-State Circuits Conference, 1998, pp. 192-193.
[10] L. Wei, Z. Chen, K. Roy, Y. Ye, V. De, “Mixed-Vth (MVT) CMOS Circuit Design Methodology for Low Power Applications” Design Automation Conference, 1999. Proceedings. 36th, Jun. 1999, pp. 430-435.
[11] F. Assaderaghi, et al., "A Dynamic Threshold Voltage MOSFET(DTMOS) for Ultra-Low Voltage Operation", IEEE International Electron Devices Meeting,
1994, pp. 809-812.
[12] F. Sill, F. Grassert, and D. Timmermann, “Low Power Gate-level Design with Mixed-Vth (MVT) Techniques”, Integrated Circuits and Systems Design, 2004. SBCCI 2004. 17th Symposium, Sep. 2004. pp. 278-282.
[13] K. Usami and M. Horowitz, “Clustered voltage scaling technique for low power
design”, in Proc. ISLPD, Apr. 1995, pp. 3–8.
[14] Y. J. Yeh, S. Y. Kuo, and J. Y. Jou, “Converter-Free Multiple-Voltage Scaling Techniques for Low-Power CMOS Digital Design”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 20, No. 1, January 2001.
[15] Standard Cell Characterization, Richard Sohnius, 16.12 2003.
[16] TSMC 0.13um (CL013G) Process 1.2-Volt SAGE-XTM Standard Cell Library Databook, Release 2.5, June 2002.
[17] UMC 90nm SP_RVT process 1.0V standard cell library databook.
[18] S. I. CHANG, J. H. LEE and H. C. SHIN, “Gate-Induced Drain Leakage Currents in Metal Oxide Semiconductor Field Effect Transistors with High-k Dielectric”, Japan J. Applied Physics, Vol. 41 Part 1, No. 7A, 15 July 2002.
[19] W. T. Kang, J. S. Kim, K. Y. Lee, Y. C. Shin, T. H. Kim, Y. J. Park, and J. W. Park, “The Leakage Current Improvement in an Ultrashallow Junction NMOS with Co Silicided Source and Drain”, IEEE Electron Device Letters, Vol. 41 Part 1, No. 7A, 15 July 2002.
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