(18.210.12.229) 您好!臺灣時間:2021/03/01 06:37
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果

詳目顯示:::

我願授權國圖
: 
twitterline
研究生:楊富明
論文名稱:前瞻非揮發性奈米晶體記憶體元件之製作與特性研究
論文名稱(外文):Fabrication and Characterization of Advanced Nonvolatile Nanocrystals Memory
指導教授:羅正忠羅正忠引用關係張鼎張
學位類別:博士
校院名稱:國立交通大學
系所名稱:電子工程系所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2007
畢業學年度:96
語文別:英文
論文頁數:100
中文關鍵詞:忍耐度保存特性記憶窗口
外文關鍵詞:enduranceretention characteristicmemory window
相關次數:
  • 被引用被引用:0
  • 點閱點閱:204
  • 評分評分:系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔
  • 下載下載:26
  • 收藏至我的研究室書目清單書目收藏:0
本論文主要是針對非揮發性奈米點記憶體元件做研究。我們成功的製作出用鈷作為奈米點的結構。鈷奈米點包含在以二氧化矽以及二氧化鉿分別當作穿遂氧化層和控制氧化層之間。通過電性分析,可以發現其具有明顯的記憶效應。在5伏特的低操作電壓下,其記憶窗口(memory window)約為1伏特左右。同時,其保存特性(retention characteristic)也相當驚人。而且,其忍耐度(endurance)在經過106次的寫入/抹除之後,也沒有衰退。
同時,我們也成功製作出以鎳奈米點當作分離式電荷儲存點記憶體,埋在二氧化矽以及二氧化鉿之間的結構。由穿遂式顯微鏡得知,鎳奈米點平均大小約為5奈米以及密度約為3.9��1012/cm2。鎳奈米點記憶體,在4伏特的寫入電壓操作下,有1伏特的切入電壓偏移(threshold voltage shift)。鎳奈米點記憶體具有很長的保存時間(retention time),極少的電荷流失率(charge loss rate)。此外,記憶體的忍耐度即使到達106次的寫入/抹除之後,也不會衰退的現象出現。
此外,我們也成功的製作以矽化鈷當作奈米點的記憶體。矽化鈷奈米點,埋在分別以二氧化矽以及二氧化鉿為穿遂氧化層和控制氧化層之間。其中我們以電子繞射圖樣分析(electron diffraction pattern),確定奈米點為矽化鈷。矽化鈷奈米點記憶體,在9伏特的電壓操作下有約為1.6伏特的切入電壓偏移。具有很長時間的保存時間且很低的電荷流失率。忍耐度即使到達106次的寫入/抹除之後也沒有變差。
同時,我們也成功製作出以矽化鎳奈米點在二氧化矽以及二氧化鉿之間的結構。在電性方面的特性可以發現有很大的記憶窗口。在操作電壓為4伏特的低電壓下,很明顯的得知有1.3伏特切入電壓偏移。這種的結構的製程將與現今半導體業界的製程相符合。
最後,在論文中我們成功的製作出多層奈米點結構的記憶體。這種多層奈米點的記憶體的優點將提高記憶體的效應。藉著增加奈米點的密度可增進保存時間的特性。雙層的奈米點記憶體比起單層的記憶體有更多的電子儲存在裡面。雙層的矽化鈷奈米點記憶體比單層的記憶體有更好的保存特性。然而,雙層結構的記憶體之所以有較佳的保存特性是因為在上層的Coulomb-blockage 效應,使得底層的電子不易流失。所以,藉由雙層的奈米點可以有效增進奈米點記憶體的記憶效應。
We have studied experimentally and theoretically nonvolatile nanocrystal memory devices. On the study of nanocrystal memory, the Co nanocrystals using SiO2 and HfO2 as the tunneling and the control dielectric with memory effect has been fabricated. A significant memory effect was observed through the electrical measurements. Under the low voltage operation of 5V, the memory window was estimated to ~ 1V. The retention characteristics were tested to be robust. Also, the endurance of the memory device was not degraded up to 106 write/erase cycles.
A distributed charge storage with Ni nanocrystals embedded in the SiO2 and HfO2 layer has been fabricated in this study. The mean size and aerial density of the Ni nanocrystals are estimated to be about 5 nm and 3.9��1012/cm2, respectively. The nonvolatile memory device with Ni nanocrystals exhibits 1 V threshold voltage shift under 4 V write operation. The device has a long retention time with a small charge lose rate. Besides, the endurance of the memory device is not degraded up to 106 write/erase cycles.
On the study of the CoSi nanocrystals with distributed charge storage elements embedded between the SiO2 and HfO2 layer has been proposed. The nanocrystals were identified to be CoSi phase by the analysis of electron diffraction pattern. The nonvolatile memory device with CoSi nanocrystals exhibits 1.6 V threshold voltage shift under 9 V write operation. The device has a long retention time with a small charge lose rate. In addition, the endurance is not degraded up to 106 write/erase cycles.
Also, a nonvolatile memory device with NiSi2 nanocrystals embedded in the SiO2 and HfO2 layer has been fabricated. A significant memory effect is observed on the characterization of the electrical properties. When a low operating voltage, 4V, is applied, a significant threshold-voltage shift of 1.3V, is observed. The processing of this structure is compatible with the current manufacturing technology of semiconductor industry.
Finally, the nonvolatile memory device with multilayer nanocrystals has advantages such as the memory effects can be increased by the increasing density of the nanocrystals and the whole retention characteristic can be improved. There are much more electrons that can be stored in the double layer than single layer nanocrystal memory device. The double layer CoSi2 nanocrystals have better retention characteristic than the single layer. The good retention characteristic of the double layer device is due to the Coulomb-blockage effects on the top layer nanocrystals from the bottom layer nanocrystals. So, the memory effects of the nonvolatile memory device can be improved by using the double layer nanocrystals.
Chinese Abstract---------------------------------------I
English Abstract--------------------------------------III
Content -----------------------------------------------VI
Acknowledgment----------------------------------------VIII
Table Captions ----------------------------------------X
Figure Captions----------------------------------------XI
Chapter 1 Introduction
1.1 General Background----------------------------------1
1.2.SONOS nonvolatile memory devices -------------------2
1.3 Nanocrystals nonvolatile memory devices-------------4
1.4 Organization of the dissertation------------------- 7
Chapter 2 Memory characteristics of Co nanocrystals memory device with HfO2 as blocking oxide
2.1 Motivation------------------------------------------14
2.2 Experimental procedures-----------------------------15
2.3 Results and discussions-----------------------------16
2.4 Conclusions ----------------------------------------19
Chapter 3 Nickel nanocrystals with HfO2 blocking oxide for nonvolatile memory application
3.1 Motivation------------------------------------------28
3.2 Experimental procedures-----------------------------29
3.3 Results and discussions-----------------------------30
3.4 Conclusions-----------------------------------------32
3.5 Retention characteristics different with Co and Ni nanocrystals memory device -----------------------------32

Chapter 4 Fabrication and electrical characteristics of CoSi nanocrystals nonvolatile memory with HfO2 blocking oxide for memory device applications
4.1 Motivation------------------------------------------43
4.2 Experimental procedures-----------------------------44
4.3 Results and discussions-----------------------------44
4.4 Conclusions-----------------------------------------46
Chapter 5 Nickel silicide nanocrystals embedded in SiO2 and HfO2 for Nonvolatile Memory Application
5.1 Motivation------------------------------------------52
5.2 Experimental procedures-----------------------------53
5.3 Results and discussions-----------------------------53
5.4 Conclusions-----------------------------------------56
Chapter 6 Using double layer CoSi2 nanocrystals to improve the memory effects of nonvolatile memory devices
6.1 Motivation------------------------------------------64
6.2 Experimental procedures-----------------------------65
6.3 Results and discussions-----------------------------66
6.4 Conclusions-----------------------------------------68

Chapter 7 Comparison electric characteristics with metal and metal-silicide nanocrystals memory device with HfO2 as blocking oxide
7.1 Motivation------------------------------------------74
7.2 Results and discussions-----------------------------74

Chapter 8 Conclusions and Suggestions for Future Work
8.1 Conclusions-----------------------------------------79
8.2 Suggestions for future work-------------------------83
References----------------------------------------------84
Vitae---------------------------------------------------99
Publication List---------------------------------------100
Chapter 1:
[1.1] D. Kahng and S. M. Sze, “A floating gate and its application to memory devices”, Bell Syst. Tech, J., 46, 1288 (1967).
[1.2] J. D. Blauwe, “Nanocrystal nonvolatile memory devices”, IEEE Transaction on Nanotechnology, 1, 72 (2002).
[1.3] M. H. White, Y. Yang, A. Purwar, and M. L. French, ”A low voltage SONOS nonvolatile semiconductor memory technology”, IEEE Int’l Nonvolatile Memory Technology Conference, 52 (1996).
[1.4] M. H. White, D. A. Adams, and J. Bu, “On the go with SONOS”, IEEE circuits & devices, 16, 22 (2000).
[1.5] H. E. Maes, J. Witters, and G. Groeseneken, Proc. 17 European Solid State Devices Res. Conf. Bologna 1987, 157 (1988).
[1.6] S. Tiwari, F. Rana, K. Chan, H. Hanafi, C. Wei, and D. Buchanan, “Volatile and non-volatile memories in silicon with nano-crystal storage”, IEEE Int. Electron Devices Meeting Tech. Dig., 521 (1995).
[1.7] J. J. Welser, S. Tiwari, S. Rishton, K. Y. Lee, and Y. Lee, “Room temperature operation of a quantum-dot flash memory”, IEEE Electron Device Lett., 18, 278 (1997).
[1.8] Y. C. King, T. J. King, and C. Hu, “MOS memory using germanium nanocrystals formed by thermal oxidation of Si1-xGex”, IEEE Int. Electron Devices Meeting Tech. Dig., 115 (1998).
[1.9] H. A. R. Wegener, A. J. Lincoln, H. C. Pao, M. R. O'Connell, R. E. Oleksiak, “The variable threshold transistor, a new electrically alterable nondestructive read-only storage device,” presented at the Internat'l Electron Devices Meeting, 1967
[1.10] Y. Yang and M. H. Write, “A low voltage SONOS nonvolatile semiconductor memory technology”, IEEE Trans. Comp. Packag., Manufact. Tech., 20, 190 (1997).
[1.11] A. Kanjilal, J. L. Hansen, P. Gaiduk, A. N. Larsen, N. Cherkashin, A. Claverie, P. Normand, E. Kapelanakis, D. Skarlatos, and D. Tsoukalas, “Structural and electrical properties of silicon dioxide layers with embedded germanium nanocrystals grown by molecular beam epitaxy,” Appl. Phys. Lett. 82, 1212 (2003).
[1.12] Y. C. King, T. J. King, and C. Hu, “MOS memory using germanium nanocrystals formed by thermal oxidation of Si Ge,” IEEE IEDM Tech. Dig., 115-118 (1998).
[1.13] F. K. LeGoues, R. Rosenberg, T. Nguyen, F. Himpsel, and B. S. Meyerson,” Oxidation studies of SiGe” J. Appl. Phys., 65, 1724 (1989).
[1.14] J. Eugene, F. K. LeGoues, V. P. Kesan, S. S. Iyer, and F. M. d’Heurle,” Diffusion versus oxidation rates in silicon-germanium alloys” Appl. Phys. Lett., 59, 78 (1991).
[1.15] V. Craciun, I. W. Boyd, A. H. Reader, and E. W. Vandenhoudt, “Low temperature synthesis of Ge nanocrystals in SiO2,” Appl. Phys. Lett. 65, 3233 (1994).
[1.16] V. Craciun, I. W. Boyd, A. H. Reader, W. J. Kersten, F. J. G. Hakkens, P. H. Oosting, and S. E. W. Vandenhoudt,” Microstructure of oxidized layers formed by the low-temperature ultraviolet-assisted dry oxidation of strained Si0.8Ge0.2 layers on Si” J. Appl. Phys., 75, 1972 (1994).
[1.17] M. Mukhopadhyay, S. K. Ray, C. K. Maiti, D. K. Nayak, and Y. Shiraki,” Properties of SiGe oxides grown in a microwave oxygen plasma” J. Appl. Phys., 78, 6135 (1995).
[1.18] J. M. Madsen, Z. Cui, and C. G. Takoudis,” Low temperature oxidation of SiGe in ozone: Ultrathin oxides” J. Appl. Phys., 87, 2046 (2000).
[1.19] H. K. Liou, P. Mei, U. Gennser, and E. S. Yang,” Effects of Ge concentration on SiGe oxidation behavior” Appl. Phys. Lett., 59, 1200 (1991).
[1.20] F. K. LeGoues, R. Rosenberg, and B. S. Meyerson, ” Dopant redistribution during oxidation of SiGe” Appl. Phys. Lett., 54, 751 (1989).
[1.21] O. Vancauwenberghe, O. C. Hellman, N. Herbots, and W. J. Tan,” New SiGe dielectrics grown at room temperature by low-energy ion beam oxidation and nitridation”, Appl. Phys, Lett., 59, 2031 (1991).
[1.22] C. Tetelin, X. Wallart, J. P. Nys, L. Vescan, and D. J. Gravesteijn, “Kinetics and mechanism of low temperature atomic oxygen-assisted oxidation of SiGe layers”, J. Appl. Phys., 83, 2842 (1998).
[1.23] F. K. LeGoues, R. Rosenberg, and B. S. Meyerson, “Kinetics and mechanism of oxidation of SiGe: dry versus wet oxidation”, Appl. Phys. Lett., 54, 644 (1989).
[1.24] M. Seck, R. A. B. Devine, C. Hernandez, Y. Campidelli, and J. C. Dupuy,” Study of Ge bonding and distribution in plasma oxides of Si1-xGex alloys” Appl. Phys. Lett., 72, 2748 (1998).
[1.25] A. Terrasi, S. Scalese, R. Adorno, E. Ferlito, M. Spadafora, and E. Rimini, ”Rapid thermal oxidation of epitaxial SiGe thin films ” Materials Science and Engineering, B89, 269 (2002).
[1.26] I. G. Kim, H. S. Kim, J. H. Lee, and H. C. Shin,” Silicon nano-crystal. memory with tunneling nitride,”” Ext. Abst. SSDM, 1998, p. 170.
[1.27]I. G. Kim, S. Y. Han, H. S. Kim, J. H. Lee, B. H. Choi, S. W. Hwang, D. Y. Ahn, and H. C. Shin,” Room temperature single electron effects in Si quantum dot memory with oxide-nitride tunneling dielectrics” IEEE Int. Electron Devices Meeting Tech. Dig., 1998, p. 111.
[1.28] Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, “Metal nanocrystal memories-part I. Device design and fabrication”, IEEE Trans. Electron Devices, 49, 1606 (2002).
[1.29] Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, “Metal nanocrystal memories-part II: electrical characteristics”, IEEE Trans. Electron Devices, 49, 1614 (2002).








Chapter 2:
[2.1] J. D. Blauwe, “Nanocrystal nonvolatile memory devices”, IEEE Transaction on Nanotechnology, 1, 72 (2002).
[2.2] S. Tiwari, F. Rana, K. Chan, H. Hanafi, C. Wei, and D. Buchanan, “Volatile and non-volatile memories in silicon with nano-crystal storage”, IEEE Int. Electron Devices Meeting Tech. Dig., 521 (1995).
[2.3] Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, “Metal nanocrystal memories-part I. Device design and fabrication”, IEEE Trans. Electron Devices, 49, 1606 (2002)..
[2.4]A. Thean and J. P. Leburton, IEEE Potentials 21, 35 (2002)
[2.5] A. Kanjilal, J. L. Hansen, P. Gaiduk, A. N. Larsen, N. Cherkashin, A. Claverie, P. Normand, E. Kapelanakis, D. Skarlatos, and D. Tsoukalas, “Structural and electrical properties of silicon dioxide layers with embedded germanium nanocrystals grown by molecular beam epitaxy,” Appl. Phys. Lett. 82, 1212 (2003).
[2.6] Y. C. King, T. J. King, and C. Hu, “MOS memory using germanium nanocrystals formed by thermal oxidation of Si1-xGex”, IEEE Int. Electron Devices Meeting Tech. Dig., 115 (1998).
[2.7]S. Tiwari, F. Rana, K. Chan, L. Shi, and H. Hanafi,” Single charge and confinement effects in nano-crystal memories” Appl. Phys. Lett. 69, 1232, (1996).
[2.8]M. Ostraat, J. De Blauwe, M. Green, D. Bell, H. Atwater, and R. Flagan,” Ultraclean Two-Stage Aerosol Reactor for Production of Oxide-Passivated Silicon Nanoparticles for Novel Memory Devices” J. Electrochem. Soc. 148, 265 (2001).
[2.9]T. C. Chang, P. T. Liu, S. T. Yan, and S. M. Sze,” Electron Charging and Discharging Effects of Tungsten Nanocrystals Embedded in Silicon Dioxide for Low-Voltage Nonvolatile Memory Technology” Electrochem. Solid-State Lett. 8, G71 (2005)
[2.10]T. C. Chang, S. T. Yan, C. H. Hsu, M. T. Tang, J. F. Lee, Y. H. Tai, P. T. Liu, and S. M. Sze,” A distributed charge storage with GeO2 nanodots” Appl. Phys. Lett. 84, 2581, (2004).
[2.11]P. H. Yeh, C. H. Yu, L. J. Chen, H. H. Wu, P. T. Liu and T. C. Chang,” Low power memory device with NiSi2 nanocrystals embedded in silicon dioxide layer”, Appl. Phys. Lett. 87, 193504 (2005).
[2.12]C. H. Lee, S. H. Hur, Y. C. Shin, J. H. Choi, D. G. Park, and K. Kim,” Charge-trapping device structure of SiO2/SiN/high-k dielectric Al2O3 for high-density flash memory” Appl. Phys. Lett. 86, 152908 (2005)
[2.13]Kow Ming Chang, “Method for forming a textured surface on a semiconductor substrate and a tunneling oxide layer on the textured surface” US Patent 6,165,844, (2000)





Chapter 3:
[3.1] M. H. White, Y. Yang, A. Purwar, and M. L. French, IEEE Int’l Nonvolatile Memory Technology Conference, 52 (1996).
[3.2] M. H. White, D. A. Adams, and J. Bu, IEEE circuits & devices, 16, 22 (2000).
[3.3] H. E. Maes, J. Witters, and G. Groeseneken, Proc. 17 European Solid State Devices Res. Conf. Bologna 1987, 157 (1988)D. Kahng and S. M. Sze,” A floating gate and its application to memory devices” Bell Syst. Tech. J. 46, 1288 (1967).
[3.4] A. Kanjilal, J. L. Hansen, P. Gaiduk, A. N. Larsen, N. Cherkashin, A. Claverie, P. Normand, E. Kapelanakis, D. Skarlatos, and D. Tsoukalas, “Structural and electrical properties of silicon dioxide layers with embedded germanium nanocrystals grown by molecular beam epitaxy,” Appl. Phys. Lett. 82, 1212 (2003).
[3.5] Y. C. King, T. J. King, and C. Hu, “MOS memory using germanium nanocrystals formed by thermal oxidation of Si1-xGex”, IEEE Int. Electron Devices Meeting Tech. Dig., 115 (1998).
[3.6] S. Tiwari, F. Rana, K. Chan, L. Shi, and H. Hanafi,” Single charge and confinement effects in nano-crystal memories” Appl. Phys. Lett. 69, 1232, (1996).
[3.7] M. Ostraat, J. De Blauwe, M. Green, D. Bell, H. Atwater, and R. Flagan,” Ultraclean Two-Stage Aerosol Reactor for Production of Oxide-Passivated Silicon Nanoparticles for Novel Memory Devices” J. Electrochem. Soc. 148, 265 (2001).
[3.8] T. C. Chang, P. T. Liu, S. T. Yan, and S. M. Sze,” Electron Charging and Discharging Effects of Tungsten Nanocrystals Embedded in Silicon Dioxide for Low-Voltage Nonvolatile Memory Technology” Electrochem. Solid-State Lett. 8, G71 (2005).
[3.9] T. C. Chang, S. T. Yan, C. H. Hsu, M. T. Tang, J. F. Lee, Y. H. Tai, P. T. Liu, and S. M. Sze,” A distributed charge storage with GeO2 nanodots” Appl. Phys. Lett. 84, 2581, (2004).
[3.10] P. H. Yeh, C. H. Yu, L. J. Chen, H. H. Wu, P. T. Liu and T. C. Chang,” Low power memory device with NiSi2 nanocrystals embedded in silicon dioxide layer”, Appl. Phys. Lett. 87, 193504 (2005).
[3.11] Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, “Metal nanocrystal memories-part I. Device design and fabrication”, IEEE Trans. Electron Devices, 49, 1606 (2002).
[3.12] C. H. Lee, S. H. Hur, Y. C. Shin, J. H. Choi, D. G. Park, and K. Kim,” Charge-trapping device structure of SiO2/SiN/high-k dielectric Al2O3 for high-density flash memory” Appl. Phys. Lett. 86, 152908 (2005).








Chapter 4:
[4.1] D. Kahng and S. M. Sze, “A floating gate and its application to memory devices”, Bell Syst. Tech, J., 46, 1288 (1967).
[4.2] J. D. Blauwe, “Nanocrystal nonvolatile memory devices”, IEEE Transaction on Nanotechnology, 1, 72 (2002).
[4.3] D. F. Bentchkowsky, Proc. IEEE, 58, 1207 (1970).
[4.4] S. Tiwari, F. Rana, K. Chan, H. Hanafi, C. Wei, and D. Buchanan, “Volatile and non-volatile memories in silicon with nano-crystal storage”, IEEE Int. Electron Devices Meeting Tech. Dig., 521 (1995).
[4.5] J. J. Welser, S. Tiwari, S. Rishton, K. Y. Lee, and Y. Lee, “Room temperature operation of a quantum-dot flash memory”, IEEE Electron Device Lett., 18, 278 (1997).
[4.6] A. Kanjilal, J. L. Hansen, P. Gaiduk, A. N. Larsen, N. Cherkashin, A. Claverie, P. Normand, E. Kapelanakis, D. Skarlatos, and D. Tsoukalas, “Structural and electrical properties of silicon dioxide layers with embedded germanium nanocrystals grown by molecular beam epitaxy,” Appl. Phys. Lett. 82, 1212 (2003).
[4.7] Y. C. King, T. J. King, and C. Hu, “MOS memory using germanium nanocrystals formed by thermal oxidation of Si1-xGex”, IEEE Int. Electron Devices Meeting Tech. Dig., 115 (1998).
[4.8] S. Tiwari, F. Rana, K. Chan, L. Shi, and H. Hanafi,” Single charge and confinement effects in nano-crystal memories” Appl. Phys. Lett. 69, 1232, (1996).
[4.9] M. Ostraat, J. De Blauwe, M. Green, D. Bell, H. Atwater, and R. Flagan,” Ultraclean Two-Stage Aerosol Reactor for Production of Oxide-Passivated Silicon Nanoparticles for Novel Memory Devices” J. Electrochem. Soc. 148, 265 (2001).
[4.10] T. C. Chang, P. T. Liu, S. T. Yan, and S. M. Sze,” Electron Charging and Discharging Effects of Tungsten Nanocrystals Embedded in Silicon Dioxide for Low-Voltage Nonvolatile Memory Technology” Electrochem. Solid-State Lett. 8, G71 (2005).
[4.11] T. C. Chang, S. T. Yan, C. H. Hsu, M. T. Tang, J. F. Lee, Y. H. Tai, P. T. Liu, and S. M. Sze,” A distributed charge storage with GeO2 nanodots” Appl. Phys. Lett. 84, 2581, (2004).
[4.12] P. H. Yeh, C. H. Yu, L. J. Chen, H. H. Wu, P. T. Liu and T. C. Chang,” Low power memory device with NiSi2 nanocrystals embedded in silicon dioxide layer”, Appl. Phys. Lett. 87, 193504 (2005).
[4.13] Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, “Metal nanocrystal memories-part I. Device design and fabrication”, IEEE Trans. Electron Devices, 49, 1606 (2002).
[4.14]陳力俊,材料電子顯微鏡學,p.75.





Chapter 5:
[5.1] J. D. Blauwe, “Nanocrystal nonvolatile memory devices”, IEEE Transaction on Nanotechnology, 1, 72 (2002).
[5.2] S. Tiwari, F. Rana, K. Chan, H. Hanafi, C. Wei, and D. Buchanan, “Volatile and non-volatile memories in silicon with nano-crystal storage”, IEEE Int. Electron Devices Meeting Tech. Dig., 521 (1995).
[5.3] Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, “Metal nanocrystal memories-part I. Device design and fabrication”, IEEE Trans. Electron Devices, 49, 1606 (2002).
[5.4] A. Kanjilal, J. L. Hansen, P. Gaiduk, A. N. Larsen, N. Cherkashin, A. Claverie, P. Normand, E. Kapelanakis, D. Skarlatos, and D. Tsoukalas, “Structural and electrical properties of silicon dioxide layers with embedded germanium nanocrystals grown by molecular beam epitaxy,” Appl. Phys. Lett. 82, 1212 (2003).
[5.5] Y. C. King, T. J. King, and C. Hu, “MOS memory using germanium nanocrystals formed by thermal oxidation of Si1-xGex”, IEEE Int. Electron Devices Meeting Tech. Dig., 115 (1998).
[5.6] S. Tiwari, F. Rana, K. Chan, L. Shi, and H. Hanafi,” Single charge and confinement effects in nano-crystal memories” Appl. Phys. Lett. 69, 1232, (1996).
[5.7] M. Ostraat, J. De Blauwe, M. Green, D. Bell, H. Atwater, and R. Flagan,” Ultraclean Two-Stage Aerosol Reactor for Production of Oxide-Passivated Silicon Nanoparticles for Novel Memory Devices” J. Electrochem. Soc. 148, 265 (2001).
[5.8] T. C. Chang, P. T. Liu, S. T. Yan, and S. M. Sze,” Electron Charging and Discharging Effects of Tungsten Nanocrystals Embedded in Silicon Dioxide for Low-Voltage Nonvolatile Memory Technology” Electrochem. Solid-State Lett. 8, G71 (2005).
[5.9] T. C. Chang, S. T. Yan, C. H. Hsu, M. T. Tang, J. F. Lee, Y. H. Tai, P. T. Liu, and S. M. Sze,” A distributed charge storage with GeO2 nanodots” Appl. Phys. Lett. 84, 2581, (2004).
[5.10] P. H. Yeh, C. H. Yu, L. J. Chen, H. H. Wu, P. T. Liu and T. C. Chang,” Low power memory device with NiSi2 nanocrystals embedded in silicon dioxide layer”, Appl. Phys. Lett. 87, 193504 (2005).
[5.11] C. H. Lee, S. H. Hur, Y. C. Shin, J. H. Choi, D. G. Park, and K. Kim,” Charge-trapping device structure of SiO2/SiN/high-k dielectric Al2O3 for high-density flash memory” Appl. Phys. Lett. 86, 152908 (2005).
[5.12] P. H. Yeh, H. H. Wu, C. H. Yu, L. J. Chen, P. T. Liu, C. H. Hsu and T. C. Chang, "Fabrication of NiSi2 Nanocrystals Embedded in SiO2 with Memory Effect by Oxidation of the Amorphous Si/Ni/SiO2 Structure" J. Vac. Sci. Technol. A 23, 851-855 (2005).
[5.13] Giuseppina Puzzilli and Fernanda Irrera,” Data retention of silicon nanocrystal storage nodes programmed with short voltage pulses” IEEE Trans. Electron Devices 53, 775(2006)
[5.14] C. J. Park, H. Y. Cho S. Kim, Suk-Ho Choi, R. G. Elliman, J. H. Han, Chungwoo Kim, H. N. Hwang and C. C. Hwang, “Annealing temperature dependence of capacitance-voltage characteristics in Ge-nanocrystal-based nonvolatile memory structures”J. Appl. Phys. 99, 036101(2006)
Chapter 6:
[6.1] S. Tiwari, F. Rana, K. Chan, H. Hanafi, C. Wei, and D. Buchanan, “Volatile and non-volatile memories in silicon with nano-crystal storage”, IEEE Int. Electron Devices Meeting Tech. Dig., 521 (1995).
[6.2] Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, “Metal nanocrystal memories-part II: electrical characteristics”, IEEE Trans. Electron Devices, 49, 1614 (2002).
[6.3] S. Tiwari, F. Rana, H. Hanafi, A. Hartstein, E. F. Crabbe, and K. Chan, “A silicon nanocrystals based memory “, Appl. Phys. Lett. 68, 1377 (1996).
[6.4] H. I. Hanafi, S. Tiwari, and I. Khan, ” Fast and long retention-time nano-crystal memory”, IEEE Trans. Electron Devices 43, 1553 (1996).
[6.5] T. C. Chang, P. T. Liu, S. T. Yan, and S. M. Sze,” Electron Charging and Discharging Effects of Tungsten Nanocrystals Embedded in Silicon Dioxide for Low-Voltage Nonvolatile Memory Technology” Electrochem. Solid-State Lett. 8, G71 (2005).
[6.6] S. Tiwari, F. Rana, K. Chan, L. Shi, and H. Hanafi,” Single charge and confinement effects in nano-crystal memories” Appl. Phys. Lett. 69, 1232, (1996).
[6.7] J. J. Welser, S. Tiwari, S. Rishton, K. Y. Lee, and Y. Lee, “Room temperature operation of a quantum-dot flash memory”, IEEE Electron Device Lett., 18, 278 (1997).
[6.8] J. D. Blauwe, “Nanocrystal nonvolatile memory devices”, IEEE Transaction on Nanotechnology, 1, 72 (2002).
[6.9] Chun-Hao Tu, Ting-Chang Chang, Po-Tsun Liu, Hsin-Chou Liu, Chia-Chou Tsai, Li-Ting Chang and Tseung-Yuan Tseng,” Formation of germanium nanocrystals embedded in silicon-oxygen-nitride layer”, Appl. Phys. Lett. 89, 052112 (2006).
[6.10] T. C. Chang, S. T. Yan, C. H. Hsu, M. T. Tang, J. F. Lee, Y. H. Tai, P. T. Liu, and S. M. Sze,” A distributed charge storage with GeO2 nanodots” Appl. Phys. Lett. 84, 2581, (2004).
[6.11] Chun-Hao Tu, Ting-Chang Chang, Po-Tsun Liu, Hsin-Chou Liu, Chi-Feng Weng, Jang-Hung Shy, Bae-Heng Tseng, Tseung-Yuan Tseng, Simon M. Sze, and Chun-Yen Chang, ”A Fabricaiton of Geemanium Nanocrystal Embedded in Silicon-Oxygen-Nitride Layer”, Electrochem. Solid-State Lett. 9, G358 (2006).
[6.12] P. H. Yeh, C. H. Yu, L. J. Chen, H. H. Wu, P. T. Liu and T. C. Chang,” Low power memory device with NiSi2 nanocrystals embedded in silicon dioxide layer”, Appl. Phys. Lett. 87, 193504 (2005).
[6.13] F. M. Yang, T. C. Chang, P. T. Liu, P. H. Yeh, Y. C. Yu, J. Y. Lin, S. M. Sze, and J. C. Lou, “Memory characteristics of Co nanocrystal memory device with HfO2 as blocking oxide”, Appl. Phys. Lett. 90, 132102 (2007)
[6.14] Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, “Metal nanocrystal memories-part I. Device design and fabrication”, IEEE Trans. Electron Devices, 49, 1606 (2002).
[6.15] Ryuji Ohba, Naoharu Sugiyama, Ken Uchida, Junji Koga, and Akira Toriumi, ”Nonvolatile Si quantum memory with self-aligned doubly-stacked dots”, IEEE Trans. Electron Devices 49, 1392 (2002).
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
系統版面圖檔 系統版面圖檔