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研究生:黃彥穎
研究生(外文):HUANG YEN YING
論文名稱:應用於SerialATA6Gb/s之展頻時脈產生器
論文名稱(外文):A Spread Spectrum Clock Generator for Serial ATA 6Gb/s Application
指導教授:周世傑周世傑引用關係
指導教授(外文):Shyh-Jye Jou
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子工程系所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2007
畢業學年度:96
語文別:英文
論文頁數:92
中文關鍵詞:鎖相迴路展頻電路
外文關鍵詞:Phase Locked Loopphase interpolationphase rotationspread spectrum clocking
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展頻技術主要是對時脈信號的頻率做調變,使得信號能量平均分散到較為寬大的頻譜內。降低其在頻譜上相對應的能量峰值。本論文先簡單的介紹鎖相迴路的設計觀念,並提出了展頻的穩態以及暫態現象的分析與鎖相迴路系統參數的關係,使得我們可以得到一個較佳的設計概念。並解決了在多工器操作之下,所造成不當的信號突波。為了保證電路操作的穩定性,我們同時採取了數位控制的解決方法,來保證相位變化是單調且一致的。在鎖相迴路中,為了減小時脈抖動,我們採取錯誤放大器的方式來解決電路操作中電流不匹配的問題,同時採用三階迴路濾波器濾除鎖相迴路中週期性的突波現象。我們在振盪器中加入被動電阻,以降低對震盪器輸入端的敏感度並提高線性度;又加入交互偶合電晶體來加速震盪器震盪轉態的操作。
我們所提出的展頻時脈產生器主要應用於Serial ATA 6Gbps中,向下展頻5000ppm同時採用三角波調變且調變頻率為30KHz。此展頻時脈產生器使用和差調變器及相位旋轉方式完成之。此電路是在90奈米互補式金氧半的製程下所製造。展頻時脈最大週期對週期時脈抖動為1.13ps並操作在1.4GHz時消耗7.57毫瓦。能量峰值所能降低的最大數量為20.6dB。晶片面積分為: 鎖相迴路主要電路 ,迴路濾波器 ,相位旋轉單位 。
Spread spectrum is to modulate the frequency of clock and to spread the clock energy in a wider spectrum. This would lead to a reduction of the peak level of the clock energy. In this thesis, we will describe the phase-locked loop (PLL) design considerations first. Then, we will introduce the steady-state and transient analysis of spread spectrum behavior. These can help us to express the SSCG design consideration with PLL parameters. We also use the interpolation technique to avoid the glitch problem due to the operation of multiplexer and provide a thermal code control to guarantee the monotonic behavior in the process of phase rotation.
In the PLL design, we achieve low jitter issue by using error amplifier to resolve the current mismatch in charge pump and a third order loop filter is adopted to reduce the reference spur. A passive resistor is presented in the VCO delay cell to reduce the Kvco gain and an additional cross-couple CMOS is also included to the delay cell to boost the operation of delay cell. Our spread spectrum clock generator (SSCG) for Serial ATA Specification is down spread 5000ppm with a triangular modulation profile and the modulation frequency is 30 kHz. A spread spectrum technique using PLL with a sigma delta modulator and phase rotation algorithm is proposed. This proposed architecture has been designed in a 90-nm CMOS process. The spread clocking has a peak-to-peak cycle-to-cycle jitter of 1.13ps and consumes 7.57mW at 1.4GHz. The EMI reduction in this circuit is about 20.6dB. The core area includes PLL Main Circuit ( ), Loop Filter ( ) and Phase Rotation Block ( ).
Contents
Chapter 1 Introduction 1
1.1 Introduction to High-Speed Serial Link 1
1.2 Timing Specifications and Application Issues 2
1.3 Motivation 5
1.4 Thesis Organization 6
Chapter 2 Principles of Phase-Locked Loop 8
2.1 Introduction to PLL 8
2.2 Analysis of PLL Linear Model 9
2.2.1 Analysis of Closed Loop Transfer Function 11
2.2.2 Analysis of Open Loop Transfer Function 13
Chapter3 Analysis of Spread Spectrum Clock Generator 18
3.1 Spread spectrum Mechanism 18
3.1.1 Introduction to Modulation Mechanism 18
3.1.2 Noise Transfer Function 21
3.2 Discrete-Time Open-Loop Criteria of PLL 23
3.3 Transient response of Spread Spectrum 28
3.3.1 Equivalent Difference Equation of SSC 28
3.3.2 Transient Response of SSC with different PLL system parameters 30
3.3.3 Effective Spread Frequency with Different Phase Jump 35
3.4 Overall Spread Spectrum Behavior 37
3.4.1 Spread Spectrum behavior without Quantization Noise 38
3.4.2 Sigma-Delta Modulation with Different Orders 42
3.4.3 Timing Impacts 47
Chapter 4 Algorithm of the Proposed Spread Spectrum Clock Generator 49
4.1 Concept of SSCG Using Phase Rotation 49
4.2 Analysis of Quantization Noise 52
4.3 Phase Rotation Mechanism 58
4.4 ΣΔ Modulator 61
Chapter 5 Circuit design of Spread Spectrum Clock Generator 64
5.1 Introduction 64
5.2 System architecture 65
5.3 Behavior Simulation 66
5.4 Circuit Implementation 68
5.4.1 Phase / Frequency Detector 69
5.4.2 Current Matching Charge Pump 70
5.4.3 3th Order Loop Filter 72
5.4.4 Voltage-Controlled Oscillator 73
5.4.5 Multiplexer and Interpolator 74
5.4.6 Divider 76
5.5 Circuit Simulation 77
5.6 Experimental Results 85
5.6.1 Layout and Pad Assignment 85
5.6.2 Measurement setup 88
Chapter 6 Conclusions 89
Reference
[1] Universal Srial Bus specification revision 2.0, Mar. 2000.
[2] R1394b Draft Standard for a High Performance Serial Bus (Supplement), P1394b Draft 1.3.1, Oct 15, 2001.
[3] Serial ATA II Electrical Specification Revision 2.5, October 27, 2005.
[4] M. Y. He and J. Poulton, “A CMOS Mixed-Signal Clock and Data Recovery Circuit for OIF CEI-6G+ Backplane Transceiver,” IEEE J. Solid-State Circuits, Vol. 41, pp. 597-606, March 2006.
[5] A. Kapoor, N. Jayakumar, and S. P. Khatri,“A novel clock distribution and dynamic de-skewing methodology,” Proc. of IEEE/ACM International Conference on Computer Aided Design, Nov. 2004, pp.626-631.
[6] R. B. Staszewski, J. L.Wallberg, S. Rezeq, C. M. Hung, O. E. Eliezer, S. K. Vemulapalli, C. Fernando, K. Maggio, R. Staszewski, N. Barton, M. C. Lee, P. Cruise, M. Entezari, K. Muhammad, and D. Leipold,“All Digital PLL and Transmitter for Mobile Phones,” IEEE J. Solid State Circuits, vol. 40, pp. 2469-2482, Dec. 2005.
[7] F. Gardner, “Charge-pump phase-lock loops,” IEEE Trans. Commun., vol.COM-28, Nov. 1980 pp. 1849–1858.
[8] H. S. Li, Y. C. Cheng, and D. Puar, “Dual-Loop Spread-Spectrum Clock Generator,” in ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 1999, pp. 184-185.
[9] S. Damphousse, K. Ouici, A. Rizki and M. Mallinson, “All digital spread spectrum clock generator for EMI reduction” IEEE J. Solid State Circuits, vol. 42, pp. 145-150, Jan. 2007.
[10] M. Kokubo, T. Kawamoto, T. Oshima, T. Noto, M. Suzuki, S. Suzuki, T. Hayasaka, T. Takahashi, and J. Kasai, “Spread-Spectrum Clock Generator for Serial ATA using Fractional PLL Controlled by ΔΣ Modulator with Level Shifter,” in ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 2005, pp. 160-161.
[11] H.R. Lee, O. Kim, G. Ahn, and D.K. Jeong, “A Low-Jitter 5000ppm Spread Spectrum Clock Generator for Multi-channel SATA Transceiver in 0.18um CMOS,” in ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 2005 pp. 162 – 163.
[12] J. Kim, M. A. Horowitz, and G.-Y. Wei, “Design of CMOS Adaptive-bandwidth PLL/DLLs: a General Approach,” IEEE Trans. Circuits Syst. II, vol. 50, pp. 860, Nov. 2003.
[13] F. Herzel and B. Razavi, "A Study of Oscillator Jitter Due to Supply and Substrate Noise," IEEE Trans. Circuits Syst. II, Vol. 46, p56-62, Jan. 1999,.
[14] S. Kim, K. Lee, Y. Moon, D. K. Jeong, Y. Choi, and H. K. Lim, “A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL,” IEEE J. Solid-State Circuits, vol. 32, pp. 691-700, May 1997.
[15] J.-S. Lee, M.-S. Keel, S.-I. Lim, and S. Kim, “Charge pump with perfect current matching characteristics in phase-locked loops,” Electron. Lett., vol. 36, no. 23, pp. 1907-1908, Nov. 2000.
[16] J. Maneatis, “Low-jitter process-independent DLL and PLL based on self-biased techniques,” in ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 1996, pp. 130–131.
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