管線式類比數位轉換器具有高速及中高解析度的特性，因此為可攜式電子產品中經常使用之架構。其可藉由低電壓及功率最佳化設計，降低電路整體功率消耗。然而，在低電壓的操作環境下, 由於信號的動態範圍減少, 電路的非理想效應會進一步劣化管線式類比數位轉換器的性能，包含飄移電壓、運算放大器的非線性增益及電容的不匹配等效應造成之增益誤差。至今，文獻上有許多校正電路技術發表, 其可藉由離線或背景補償等方式, 提升轉換器電路之性能。

本論文提出一個 1 伏特, 9 位元之管線式類比數位轉換器。 為改善低電壓操做運算放大器之增益與頻寬, 本論文提出轉導分離式運算放大器電路, 其在相同之功率消耗與單位增益頻寬之下, 可提升增益達 10 dB。此外, 為克服低電壓操做運算放大器之有限增益效應, 本架構內含運算放大器及倍乘數位類比轉換器(M-DAC) 之增益萃取電路, 本論文並提出偏移誤差補償方法, 以大達幅提高運算放大器增益萃取之準確性, 藉由離線補償可提升整體轉換器之有效位元數達2位元。

本實驗晶片以0.18μm CMOS 製程實作完成, 晶片面積為1.45×1.55 mm2。本電路採用雙重取樣技術以提升運算放大器之使用效率, 同時倍增取樣率, 其轉換率可達每秒八十百萬次取樣。量測結果顯示其微分和積分非線性誤差(Differential and Integral Nonlinearity)分別為+1.1/-0.8LSB和+1.3/-1.3LSB。 本轉換器之核心電路皆操作在 1 伏特工作電壓, 整體功率消耗為 11.5mW， 其 FOM值達 0.88pJ/conversion。

Pipelined ADCs are widely applied in portable electronic devices thanks to its features of high speed operation and medium to high resolution in data conversion. Its power dissipation can be further reduced by applying low voltage and power scaling techniques. However, the dynamic range of the input signal is severely limited under a low supply voltage. The non-idealities of the data converter, such as offset voltage and gain error caused by OP gain nonlinearities and capacitor mismatches, will further degrade its overall performance. Nowadays, several calibration techniques have been proposed in the literature. The performance of the data converter can be enhanced by means of off-line or background calibrations.

This thesis proposes a 1 V, 9bits pipelined ADC. In order to improve the gain bandwidth performance of the operational amplifier under a low supply voltage, a novel OPAMP with split transconductance input stage is proposed. It can boost the conversion gain by 10dB under a given current consumption and without degrading its unity-gain bandwidth performance. Besides, in order to eliminate the OP finite gain effect under a 1 V supply, on-chip calibration circuits are incorporated to extract the conversion gain of the OP and MDAC. Furthermore, input offset cancellation techniques are proposed to improve the accuracy of the calibration circuits. The effective number of bits (ENOB) of the data converter can be improved by 2 bits by applying offline calibration.

The experimental prototype has been fabricated in a 0.18μm CMOS technology, the chip size is 1.55×1.45mm2. Double-sampling technique is applied to improve the power efficiency of the OPAMs as well as double the conversion rate. Experimental results reveal that the DNL and INL are +1.1/-0.8LSB and +1.3/-1.3LSB respectively at 80 MS/s. All the core circuits are operated under a 1 V supply, and the total power consumption is 11.5 mW. The corresponding FOM (Figure of Merit) is 0.88pJ/conversion.

INTRODUCTION 1
1.1 Motivation 1
1.2 Thesis Organization 2
CHAPTER 2 4
NYQUIST RATE DATA CONVERTER 4
2.1 Introduction 4
2.2 ADC Performance Metrics 4
2.2.1 Resolution 4
2.2.2 Signal-to-Noise Ratio (SNR) 5
2.2.3 Spurious Free Dynamic Range (SFDR) and Signal to Noise Distortion Ratio (SNDR) 7
2.2.4 Dynamic Range(DR) 8
2.2.5 Imperfections 9
2.2.6 Differential Non-Linearity (DNL) and Integral Non-Linearity (INL) 10
2.3 Review of ADC Architecture 11
2.3.1 Flash ADC 11
2.3.2 Cyclic ADC 13
2.3.3 Pipelined ADC 13
2.4 Design Issue of Pipelined ADC 16
2.4.1 Stage Accuracy and Speed Requirement 16
2.4.2 Double Sampling 18
2.4.3 Power Optimization 18
2.5 MATLAB Behavior Model 19
CHAPTER 3 22
CIRCUIT SPECIFICATION 22
AND 22
SIMULAION 22
3.1 Time-interleaved Pipelined ADC Design 22
3.1.1 Design Issue 22
3.1.2 Architecture 23
3.2 Each Block of Pipelined ADC 24
3.2.1 Operational Amplifier 24
3.2.2 Common Mode Feedback Cicruit (CMFB) 27
3.2.3 Comparator 29
3.2.4 The 1.5 bit flash ADC 31
3.2.5 Flip-around DAC (FADAC) 32
3.2.6 Bootstrapped Switch 35
3.2.7 Multiply DAC (MDAC) 37
3.2.8 Double Sampling 38
3.2.9 Final 2bit flash ADC 39
3.2.10 Clock Generator 40
3.2.11 Timing Diagram 41
CHAPTER 4 43
CALIBRATION CIRCUIT 43
4.1 Calibration Conception 43
4.1.1 Nonlinearity of gain 44
4.2 Calibration Circuit 46
4.3 Operation Amplifier in Calibration Circuit 47
4.4 Calibration Circuit with Offset Cancellation 49
4.5 Simulation Result 52
CHAPTER 5 54
EXPERIMENTAL RESULT 54
5.1 Floor-planning and Layout 54
5.2 System Simulation Result 55
5.2.1 Time domain Simulation 55
5.2.2 Dynamic Simulation 55
5.2.3 INL and DNL 59
5.2.4 Dynamic Range 60
5.2.5 Specification Table 61
5.3 Experimental Result 62
5.3.1 Measurement Consideration 62
5.3.2 Experimental Result 63
CHAPTER 6 68
CONCLUSION 68
REFERENCE 70

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