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研究生:洪潤傑
研究生(外文):Junchieh Hung
論文名稱:IEEE802.16eOFDMA下行同步技術之探討與數位訊號處理器實現
論文名稱(外文):Research in and DSP Implementation of Synchronization Techniques for IEEE 802.16e OFDMA Downlink
指導教授:桑梓賢
指導教授(外文):Tzuhsien Sang
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子工程系所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2007
畢業學年度:96
語文別:英文
論文頁數:66
中文關鍵詞:下行同步技術探討數位訊號處理器實現
外文關鍵詞:ResearchDSPImplementationSynchronizationTechniquesIEEE802.16eOFDMADownlink
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本篇論文提出IEEE 802.16e正交分頻多工存取(OFDMA)下行(downlink)過程中起始同步的機制,包含符碼時間偏移、載波偏移的同步與基地台(cell)同步碼索引(preamble index)的識別。當一個行動電話在一開始要進入網路的時候,我們必須做起始的同步。我們提出的方法不需要傳送端同步碼的訊息,只需利用同步碼的結構、循環字首(cyclic prefix)以及傅立葉轉換(Fourier transform)的性質,即可做到時間和頻率的同步,與基地台同步碼索引的識別。而在之後的次訊框裡,行動電話只需要做到追蹤符碼時間偏移和小數部分載波偏移即可。
我們首先用浮點數運算來驗證起始同步的技術,並在多路徑Rayleigh 衰減通道下做模擬,模擬速度大約120 km/h,並觀察其結果。最後,我們選擇最適合我們系統的同步演算法,並把這些方法修改成定點運算的版本,實現在數位訊號處理(DSP)平台上。
In this thesis, we propose an initial synchronization scheme for time, carrier frequency synchronization and cell preamble index identification in 802.16e OFDMA downlink. In DL synchronization, the mobile station receiver needs to perform initial synchronization upon its initial entrance to the network. The proposed method does not require knowledge of actual transmitted preamble, but only utilizes the preamble structure, CP, and inverse Fourier transform properties to obtain time/frequency synchronization and cell preamble index identification. Then in subsequent sub-frame, the mobile station only needs to track the timing and fractional CFO.
We verify the initial synchronization techniques in floating point computation, simulate in multi-path Rayleigh fading channel which the speed is about 120 km/h, and see the performance. In the end, we choose the most suitable methods for our system into fixed point version on the DSP platform.
Chapter 1 Overview of Physical Layer (PHY) IEEE 802.16e OFDMA................1
1.1 Introduction to OFDM and OFDMA Systems....................................1
1.2 Introduction to Mobile WiMAX...........................................................3
1.3 Introduction to IEEE 802.16e Downlink..............................................4
1.3.1 OFDMA Frame Structure............................................................4
1.3.2 OFDMA Symbol Structure...........................................................5
Chapter 2 Synchronization Techniques for IEEE 802.16e Downlink...................8
2.1 Channel Model and System Parameters..............................................8
2.1.1 Modified Stanford University Interim (SUI) Channel Models.8
2.1.2 System Parameters.......................................................................11
2.2 Synchronization Control Mechanisms...............................................13
2.2.1 Network Synchronization...........................................................13
2.2.2 SS Synchronization.....................................................................13
2.2.3 Frequency Control Requirements.............................................14
2.3 Mobile Station Synchronization Techniques......................................15
2.3.1 Symbol Timing Estimation.........................................................16
2.3.2 Fractional CFO Estimation........................................................25
2.3.3 Integer CFO Estimation and Preamble Index Identification..30
Chapter 3 DSP Implementation of IEEE 802.16e Downlink System..................36
3.1 Introduction to the DSP Platform.......................................................36
3.1.1 MSC8126ADS Board Architecture............................................36
3.1.2 MSC8126 Features......................................................................38
3.1.3 Developing Optimized Code for Speed on SC140 Cores.........41
3.2 Implementation of Transmitter...........................................................43
3.3 Performance Analysis of Synchronization Implementation.............50
3.3.1 Symbol Timing Estimation.........................................................50
3.3.2 Fractional CFO Estimation........................................................52
3.3.3 Summary of Implementation Analysis for Synchronization...54
3.3.4 Integer CFO Estimation and Preamble Index Identification..58
3.4 WiMAX System Integration on the DSP Platform...........................60
Chapter 4 Conclusions and Future Work..............................................................62
4.1 Conclusions...........................................................................................62
4.2 Future Work.........................................................................................63
Bibliography 64
About the Author 66
[1] J. Heiskala, J. Terry, OFDM Wireless LANs: A Theoretical and Practical Guide. Indiana: SAMS, 2001.
[2] R. van Nee and R. Prasad, OFDM for Wireless Multimedia Communications. Boston: Artech House, 2000.
[3] WiMAX Forum, “MobileWiMAX—Part 1: A technical overview and performance evaluation,” June 2006.
[4] IEEE Std 802.16-2004, IEEE Standard for Local and Metropolitan Area Networks — Part 16: Air Interface for Fixed Broadband Wireless Access Systems. New York: IEEE, June 2004.
[5] IEEE Std 802.16e-2005 and IEEE Std 802.16-2004/Cor1-2005, IEEE Standard for Local and Metropolitan Area Networks—Part 16: Air Interface for Fixed Broadband Wireless Access Systems—Amendment 2: Physical and Medium Access Control Layers for Combined Fixed and Mobile Operation in Licensed Bands and Corrigendum 1. New York: IEEE, Feb. 28, 2006.
[6] V. Erceg et al., “Channel models for fixed wireless applications,” IEEE 802.16.3c- 01/29r4, July 2001.
[7] Y.-C. Liu, D. W. Lin, “Research in and DSP implementation of synchronization techniques for IEEE 802.16e,“ M.S. thesis, Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan, R.O.C., June 2007.
[8] T. Bhatt, V. Sundaramurthy, J. Zhang, D. McCain “Initial synchronization for 802.16e downlink,” Proc. Asilomar Conf. Signals Systems Computers., Nov. 2006, pp. 701-706.
[9] J.-J.van de Beek, M. Sandell, “ML estimation of time and frequency offset in OFDM systems,” IEEE Trans. On Signal Processing, Vol. 45, No. 7, July 1997.
[10] Freescale Semiconductor, MSC8126 Reference Manual. Literature number MSC8126RM, April 2005.
[11] Freescale Semiconductor, MSC8126ADS Product Brief. Literature number MSC8126ADSPB, Jan. 2005.
[12] Freescale Semiconductor, Developing Optimized Code for Both Size and Speed on the StarCore SC140/SC1400 Cores. Literature number AN2266, Nov. 2004.
[13] R. Andraka, “A survey of CORDIC algorithms for FPGA based computers,” FPGA 98 Monterey CA USA.
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