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研究生:張子恒
研究生(外文):Tzu-Heng Chang
論文名稱:利用濕式氧化氮化矽層改善氧化矽/氮化矽/氧化矽堆疊結構型快閃記憶體之研究
論文名稱(外文):Study on the Improvement of ONO-stacked Flash Memory by Wet Oxidation of Si3N4 Layer
指導教授:雷添福
指導教授(外文):Tan-Fu Lei
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子工程系所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
畢業學年度:96
語文別:英文
論文頁數:79
中文關鍵詞:濕式氧化氧化矽/氮化矽/氧化矽快閃記憶體
外文關鍵詞:wet oxidationSONOSflash memorynano-crystals
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此論文主要是在研究利用濕式氧化法來製作SONOS型非揮發性快閃記憶體其中的阻障層(blocking layer)。現今大多數的人都使用沉積方式去堆疊阻障層的氧化層,此論文採用的方式是直接在沉積捕陷電荷層(trapping layer)後,直接將捕陷電荷層氮化矽 (Si3N4) 材料濕式氧化,來製備阻障層。更進一步的配合捕陷電荷層的改善,以達成有快速寫入抹除速度、且良好的儲存資料持久性、以及寫入、清除操作造成的性能退化少的非揮發性快閃記憶體。
首先,我們直接利用濕式氧化去氧化氮化矽去形成阻障層的二氧化矽,可望利用在氧化時,氧分子可以有比較快的擴散速度,擴散至氮化矽中,進而填補較淺的捕捉態(trap state),只留下較深處的捕捉態,這樣一來便可增加此記憶體元件的可靠度。
接著,我們為了增加氧化氮化矽的速度,希望在氮化矽上層提供矽原子來氧化。利用了兩種不同的方式,其一是在氮化矽上層堆疊一層很薄的非晶矽(amorphous-Si)當作犧牲氧化層(sacrificial layer )。成功的改善了氧化的速度,這種製程方式會因為沉積很薄的非晶矽,而造成之後的上氧化層會很凹凸不平,可由原子力顯微鏡(atomic force microscopy, AFM)及穿透式電子顯微鏡(transmission electron microscopy, TEM)來證明。電場在此處的分佈就很不平均,所以此結構的記憶體元件提供了另一種寫入及抹除的機制,電子改成利用上氧化層來進入捕陷電荷層,卻亦可維持可接受的可靠度。
最後,另一種方式是利用氮化矽層內嵌奈米矽晶體(Si nano-crystals )來提供矽原子的成分。在不同高度的氮化矽中放入奈米矽晶體,會因為是否被氧化到而有不同的特性改善,在放入奈米矽晶體的元件中,若矽晶體在氧化的範圍之內,便可很明顯的在可靠度方面得到很好的改善。且在氮化矽上放入矽晶體後,在電荷儲存方式便可更加區域性,使其一個單元儲存兩個位元(two bit per cell),我們可成功的設計出寫入及取讀條件,並且在儲存兩個位元的時候,依舊可以保持很好的儲存資料持久性。
In this thesis, we mainly study on using wet oxidation to form the blocking layer of the SONOS (poly Si-oxide-nitride-oxide-silicon) type nonvolatile flash memory. Generally, the blocking oxide layers are mostly deposited by furnace. We adopt another way that is the deposited nitride trapping layer was directly oxidized by wet oxidation to form the blocking oxide layer. This nonvolatile memory structure with some changes in trapping layer will have superior characteristics in terms of considerably high speed program/erase, long retention time, and excellent endurance.
First, we present a nonvolatile SONOS type flash memory that was fabricated using wet oxidation to form the oxide layer as the blocking layer from the trapping layer. Oxygen may diffuse faster into the nitride layer, and it can passivate the shallow trap states in nitride. Therefore, there were only the deeper trap states in the trapping layer, and this kind of memory device may have better reliability.
Then, the silicon atoms were provided in the nitride or on top of it for raising the wet oxidation rate. There are two different methods. One of them is that a thin amorphous silicon layer was deposited as the sacrificial layer on the nitride layer. This method successfully improves the oxidation rate. At the same time, the method would form a rough top oxide layer. We can use atomic force microscopy (AFM) and transmission electron microscopy (TEM) to check it. This memory structure would provide another program/erase mechanism, because the electric field was different in the top oxide layer. The electrons injected into the trapping layer through the top oxide layer instead of the bottom oxide layer. This memory still maintains a good reliability.
Finally, the other way is that the silicon source was introduced into the nitride by embedded silicon nano-crystals. Different heights of silicon nano-crystals determine if they are oxidized or not, which results in different improvements. Embedded silicon nano-crystals may improve the reliability or localize the trapping sites. This memory structure can use two bit operation, and still keep good retention.
Contents
Abstract (Chinese) ………………I
Abstract (English) ………………III
Acknowledge ……………… V
Contents ………………VI
Figure Captions & Table Lists ………………VIII

Chapter 1 Introduction ………………1
1.1 Background…………………1
1.2 Motivation…………………5
1.3 Thesis Organization …………………6
1.4 Reference…………………12

Chapter 2 Physical and Electrical Properties of SONOS Memory Using Wet Oxidation………………15
2.1 Introduction …………………15
2.2 Experimental …………………16
2.3 Results and discussion…………………17
2.3.1 Material Analysis of Memory Device …………………17
2.3.2 Characteristics of Fresh Device…………………18
2.3.3 Characteristics after P/E Cycling and Disturbance…………………18
2.4 Summary…………………19
2.5 Reference…………………33

Chapter 3 Physical and Electrical Properties of SONOS Memory Using Wet Oxidation with Sacrificial Silicon Layer………………35
3.1 Introduction…………………35
3.2 Experimental…………………36
3.3 Results and Discussion…………………37
3.3.1 Analysis the Structure of Top Oxide Layer…………………37
3.3.2 Operation of SONOS Memory with Textured Oxide…………………38
3.3.3 Characteristics of P/E Cycling…………………39
3.4 Summary…………………40
3.5 Reference…………………51

Chapter 4 Characteristics of SONOS Memory Using Wet Oxidation with Embedded Silicon Nano-crystals in Nitride Layer………………53
4.1 Introduction…………………53
4.2 Experimental…………………54
4.3 Results and Discussion…………………55
4.3.1 Material Analysis of Memory Device………………….55
4.3.2 Characteristics of Fresh Device…………………55
4.3.3 Characteristics after P/E Cycling and Disturbance…………………56
4.3.4 Two-bit operation and migration of charges storage…………………58
4.4 Summary …………………59
4.5 Reference…………………77

Chapter 5 Conclusions………………79
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