臺灣博碩士論文加值系統

本論文提出了一個可重組態之低功率快速傅立葉轉換處理器，此記憶體式架構之處理器能夠處理64到8192點的傅立葉轉換。此外，本篇論文提出了一個藉由改變傅立葉係數之順序而達到最小化switching activity的方法。藉由 Synopsys Design Complier的合成，在UMC 0.18 um COMS 的製程環境下，所提出之設計在不包含記憶體的情況下僅需53306個邏輯閘，並且在1.8伏特之電壓源供應下，僅有75.82毫瓦的低功率消耗。

In this thesis, a low power reconfigurable FFT processor is proposed. The memory based FFT can be configured as from 64-point to 8192-point. Besides, a modified coefficient ordering method with minimum switching activity is proposed for low power design. The switching activity of twiddle factor computation can be reduced from 633 to 480 at the first stage of 64-point and 139 to 0 at the first stage of 16-point. The proposed design synthesized to UMC 0.18um CMOS standard cell technology library with Synopsys Design Compiler. The gate count of the proposed architecture without ram is 53306 at 111 MHz clock rate and power consumption is 75.82 mW at power supply 1.8 V.

摘要 i
Abstract ii
Contents iv
List of Figures vi
List of Tables viii
Chapter 1. Introduction. 1
1.1. Motivation 1
1.2. Discrete Fourier Transform 2
1.3. Introduction to FFT algorithm 3
1.4. Introduction to FFT architecture 6
1.4.1. Memory based FFT architecture 7
1.4.2. Pipeline based FFT architecture 8
1.4.3. Summary 9
Chapter 2. Low Power Design 10
2.1. Introduction to Switching Activity 10
2.2. Minimum Switching Activity 13
2.2.1 Minimum switching activity of 16-point FFT 13
2.2.2 Minimum switching activity of 64-point FFT 18
2.3. Summary 23
Chapter 3. Proposed architecture 27
3.1. Design issue 28
3.2. Radix-2/4 Butterfly 29
3.3. Multiplier module 30
3.4. Phase Compensator 32
3.5. Memory Address Assignment 33
Chapter 4. Simulation and Performance Analysis 35
4.1. Simulation 36
4.2. FPGA prototyping 39
4.3. Synthesis Reports and Power Analysis 49
4.4. Comparisons 51
Chapter 5. 52
Bibliography 53
Vita 55

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