跳到主要內容

臺灣博碩士論文加值系統

(18.97.14.84) 您好!臺灣時間:2024/12/04 11:26
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

: 
twitterline
研究生:廖述穎
論文名稱:鉬奈米點在非揮發性記憶體應用之研究
論文名稱(外文):Study on Floating-Gate Molybdenum Nanocrystals for Nonvolatile Memory Application
指導教授:施敏施敏引用關係
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子工程系所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:96
語文別:英文
論文頁數:72
中文關鍵詞:記憶體
外文關鍵詞:Momemory
相關次數:
  • 被引用被引用:0
  • 點閱點閱:200
  • 評分評分:
  • 下載下載:13
  • 收藏至我的研究室書目清單書目收藏:0
非揮發性記憶體(NVM)目前在元件尺寸持續微縮下的需求為高密度記憶單元、低功率損耗、快速讀寫操作、以及良好的可靠度(Reliability)。傳統浮動閘極(floating gate)記憶體在操作過程中如果穿隧氧化層產生漏電路徑會造成所有儲存電荷流失回到矽基板,所以在資料保存時間(Retention)和耐操度(Endurance)的考量下,很難去微縮穿隧氧化層的厚度。非揮發性奈米點記憶體被提出希望可取代傳統浮動閘極記憶體,由於奈米點可視為電荷儲存層中彼此分離的儲存點,可以有效改善小尺寸記憶體元件多次操作下的資料儲存能力。近年來發展了許多方法來形成奈米點,一般而言,大多數的方法都需要長時間高溫的熱製程,這個步驟會影響現階段半導體製程中的熱預算和產能。
在本文中,一個簡單的製程方法用來形成鉬(Molybdenum)奈米點,並應用於非揮發性記憶體。室溫下,共蒸鍍(co-evaporating)鈀材Mo和介電質(如:SiOx、SiNx、AlOx)形成介電質包覆著鉬奈米點的非揮發性記憶體結構,我們認為在退火過程中形成奈米點,溫度扮演一個重要的腳色,可以簡單並均勻地形成高密度(~1012 cm-2)的奈米點。我們發現高密度的鉬奈米點被包覆在氧化鋁(AlOx)中有較好的儲存能力。此外,這個應用在非揮性記憶體的製程技術同時也適用於現階段積體電路製程。
Current requirements of nonvolatile memory (NVM) are the high density cells, low-power consumption, high-speed operation and good reliability for the scaling down devices. However, all of the charges stored in the floating gate will leak into the substrate if the tunnel oxide has a leakage path in the conventional NVM during endurance test. Therefore, the tunnel oxide thickness is difficult to scale down in terms of charge retention and endurance characteristics. The nonvolatile nanocrystal memories are one of promising candidates to substitute for conventional floating gate memory, because the discrete storage nodes as the charge storage media have been effectively improve data retention under endurance test for the scaling down device. Many methods have been developed recently for the formation of nanocrystal. Generally, most methods need thermal treatment with high temperature and long duration. This procedure will influence thermal budget and throughput in current manufacture technology of semiconductor industry.
In this thesis, an ease fabrication technique of molybdenum nanocrystals was demonstrated for the application of nonvolatile memory. The nonvolatile memory structure of molybdenum nanocrystals embedded in the dielectric layer was fabricated by co-evaporating molybdenum and dielectric which like SiOx, SiNx and AlOx at room temperature. It can be considered that the annealing tamperature plays a critical role during sputter process for the formation of nanocrystal. In addition, the high density (~1011 cm-2) nanocrystal can be simple and uniform to be fabricated in our study. We also proposed a formation of molybdenum nanocrystals embedded in AlOx by co-evaporating molybdenum and AlOx at room temperature. It was also found that high density Mo nanocrystals embedded in theAlOx and larger memory effect. These fabrication techniques for the application of nonvolatile nanocrystal memory can be compatible with current manufacture process of the integrated circuit manufacture.
Chinese Abstract Ⅰ
English Abstract Ⅱ
Acknowledgement Ⅳ
Contents Ⅴ
Table Captions Ⅸ
Figure Captions Ⅹ

Chapter1 Introduction
1.1 Overview of Nonvolatile Memory 1
1.1.1 SONOS Nonvolatile Memory Devices 2
1.1.2 Nanocrystal Nonvolatile Memory Devices 4
1.2 Organization of This Thesis 8

Chapter2 Basic Principle of Nonvolatile Memory
2.1 Introduction 13
2.2 Basic Program/Erase Mechanisms 14
2.2.1 Energy band diagram during program and erase
operation 14
2.2.2 Carrier injection mechanisms 14
2.3 Basic Reliability of Nonvolatile Memory 18
2.3.1 Retention 19
2.3.2 Endurance 19
2.4 Basic Physical Characteristic of Nanocrystal NVM
20
2.4.1 Quantum Confinement Effect 20
2.4.2 Coulomb Blockade Effect 20


Chapter 3 Formation and Nonvolatile Memory Effect of Mo Nanocrystal embedded in SiOx
3.1 Motivation 32
3.2 Nonvolatile Molybdenum Nanocrystal Memory by
oxidation Mo and Si layer 32
3.2.1 Experimental Procedures 32
3.2.2 Results and Discussions 33
3.3 Nonvolatile Mo Nanocrystal Memory by thermal annealing Mo and SiO2 layer 33
3.3.1 Experimental Procedures 34
3.3.2 Results and Discussions 36
3.4 Comparison of Electrical Characteristics between Mo nanocrystal by oxidizing
Mo-Si and annealing Mo-SiO2 36
3.5 Summary I 37

Chapter4 Formation and Nonvolatile Memory Effect of Mo Nanocrystal embedded in SiNx
4.1. Motivation 44
4.2. Nonvolatile Molybdenum Nanocrystal Memory by
oxidation Mo and SiNx layer 44
4.2.1 Experimental Procedures 44
4.2.2 Results and Discussion 45
4.3. Comparison of Electrical Characteristics between
Molybdenum Nanocrystals embedding in SiOx and SiNx
Nonvolatile Memory 46
4.4. Summary II 47

Chapter5 Formation and Nonvolatile Memory Effect of Mo
Nanocrystal embedded in AlOx
5.1 Motivation 54
5.2 Nonvolatile Molybdenum Nanocrystal Memory by
oxidation Mo and AlOx layer 54
5.2.1 Experimental Procedures 54
5.2.2 Results and Discussion 55
5.3 Comparison of Electrical Characteristics between
Molybdenum Nanocrystals embedding in SiOx and AlOx
Nonvolatile Memory 56
5.4 Summary Ⅲ 57

Chapter 6 Conclusion
6.1 Conclusions 63

References 65
Chapter 1

[1.1] S. Lai, Future Trends of Nonvolatile Memory Technology, December 2001.
[1.2] S. Aritome, IEEE IEDM Tech. Dig., 2000, p.763.
[1.3] P. Pavan, R. Bez, P. Olivo, and E. Zanoni, “Flash memory cells—An overview” Proc. IEEE, vol. 85, pp. 1248–1271, Aug. 1997.
[1.4] Roberto Bez, Emilio Camerlenghi, Alberto Modelli, and Angelo Visconti, “Introduction to Flash Memory” Proc. IEEE, vol. 91, NO.4, April 2003.
[1.5] D. Kahng and S. M. Sze, “A floating gate and its application to memory devices”, Bell Syst. Tech, 46, 1288 (1967).
[1.6] J. D. Blauwe, “Nanocrystal nonvolatile memory devices”, IEEE Transaction on Nanotechnology, 1, 72 (2002).
[1.7] M. H. White, Y. Yang, A. Purwar, and M. L. French, ”A low voltage SONOS nonvolatile semiconductor memory technology”, IEEE Int’l Nonvolatile Memory Technology Conference, 52 (1996).
[1.8] M. H. White, D. A. Adams, and J. Bu, “On the go with SONOS,” IEEE circuits & devices, 16, 22 (2000).
[1.9] H. E. Maes, J. Witters, and G. Groeseneken, Proc. 17 European Solid State Devices Res. Conf. Bologna 1987, 157 (1988).
[1.10] S. Tiwari, F. Rana, K. Chan, H. Hanafi, C. Wei, and D. Buchanan, “Volatile and non-volatile memories in silicon with nano-crystal storage”, IEEE Int. Electron Devices Meeting Tech. Dig., 521 (1995).
[1.11] J. J. Welser, S. Tiwari, S. Rishton, K. Y. Lee, and Y. Lee, “Room temperature operation of a quantum-dot flash memory”, IEEE Electron Device Lett., 18, 278 (1997).
[1.12] Y. C. King, T. J. King, and C. Hu, “MOS memory using germanium nanocrystals formed by thermal oxidation of Si1-xGex”, IEEE Int. Electron Devices Meeting Tech. Dig., 115 (1998).
[1.13] H.A.R. Wegener, A.J. Lincoln, H.C. Pao, M.R. O’Connell, and R.E. Oleksiak, The variable threshold transistor, a new electrically alterable, non-destructive read-only storage device,” IEEE IEDM Tech. Dig., Washington, D.C., 1967.
[1.14] T.Y.Chan, K.K.Young and C.Hu, “A true single-transistor oxide- nitride-oxide EEPROM device”. IEEE Electron Device Letters, vol.8, no.3, pp.93-95, 1987.
[1.15] M.K. Cho and D.M.Kim, “High performance SONOS memory cells free of drain turn-on and over-erase: compatibility issue with current flash technology”, IEEE Electron Device Letters, pp.399-401, Vol.21, No.8, 2000.
[1.16] I. Fijiwara, H.Aozasa, K.Nomoto, S.Tanaka and T.Kobayashi, “ High speed program/erase sub 100nm MONOS memory cell”, Proc. 18th Non-Volatile Semiconductor Memory Workshop, p. 75, 2001.
[1.17] H. Reisinger, M. Franosch, B. Hasler, and T. Bohm, Symp. on VLSI Tech. Dig. ,
9A-2, 113 (1997).
[1.18] C. Tung-Sheng, W. Kuo-Hong, C. Hsien, and K. Chi-Hsing, “Performance improvement of SONOS memory by bandgap engineering of charge-trappinglayer”, IEEE Electron Device Lett., vol. 25, no. 3, pp.205–207, Mar. 2004.
[1.19] Y. N. Tan, W. K. Chim, and B. J. Cho, W. K. Choi, “Over-Erase Phenomenon in SONOS-Type Flash Memory and its Minimization Using a Hafnium Oxide Charge Storage Layer”, IEEE Transations on Eelectron Devices, vol.51, no.7, July 2004.
[1.20] Min She, Hideki Takeuchi, and Tsu-Jae King, “Silicon-Nitride as a Tunnel Dielectric for Improved SONOS-Type Flash Memory”, IEEE Electron Device Letters, vol. 24, no. 5, MAY 2003.
[1.21] Chang-Hyun Lee, Kyu-Charn Park, and Kinam Kim, “Charge-trapping memory cell of SiO2/SiN/high-k dielectric Al2O3 with TaN metal gate for suppressing backward-tunneling effect”, Applied Physics Letters 87, 073510 (2005)
[1.22] Shih-Ching Chen, Ting-Chang Chang, Po-Tsun Liu, Yung-Chun Wu, and Ping-Hung Yeh, “Nonvolatile polycrystalline silicon thin-film-transistor memory with oxide/nitride/oxide stack gate dielectrics and nanowire channels”, Applied Physics Letters 90, 122111 (2007)
[1.23] Peiqi Xuan, Min She, Bruce Harteneck, Alex Liddle, Jefkey Bokor, and Tsu-Jae King, “FinFET SONOS Flash Memory for Embedded Applications”, IEEE IEDM 609-612 (2003).
[1.24] Tzu-Hsuan Hsu, Hang Ting Lue, Ya-Chin King, Jung-Yu Hsieh, Erh-Kun Lai, Kuang-Yeu Hsieh, and Chih-Yuan Lu, “A High-Performance Body-Tied FinFET Bandgap Engineered SONOS (BE-SONOS) for NAND-Type Flash Memory”, IEEE Electron Device Letters, vol. 28, no. 5, MAY 2007.
[1.25] S. Tiwari, F. Rana, K. Chan, H. Hanafi, W. Chan, and Doug Buchanan, IEDM Tech. Dig., p.521 (1995)
[1.26] J De Blauwe, “Nanocrystal nonvolatile memory devices”, IEEE Trans. Nanotechnol, 2002.
[1.27] R. Ohba, N. Sugiyama, K. Uchida, J. Koga, and A. Toriumi, IEEE Trans. Electron Devices 49, 1392 (2002).
[1.28] Y. C. King, T. J. King, and C. Hu, IEEE Trans. Electron Devices 48, 696 (2001)
[1.29] Y. Shi et al., in Proceedings of the First Joint Symposium on Opto- and Microelectronic Devices and Circuits, 2000, pp. 142–145.
[1.30] H. G. Yang, Y. Shi, S. L. Gu, B. Shen, P. Han, R. Zhang, and Y. D. Zhang, Microelectron. J. 34, 71 (2003).
[1.31] Zengtao Liu, Chungho Lee, Venkat Narayanan, Gen Pei, and Edwin Chihchuan Kan, “Metal Nanocrystal Memories—Part I: Device Design and Fabrication”, IEEE Trans. Electron Devices, VOL. 49, NO. 9, SEPTEMBER 2002.
[1.32] Chungho Lee, Udayan Ganguly, Venkat Narayanan, and Tuo-Hung Hou, “Asymmetric Electric Field Enhancement in Nanocrystal Memories”, IEEE Eelectron Electron Letters, vol. 26, NO. 12, DECEMBER 2005.
[1.33] Jong Jin Leea, Yoshinao Harada Jung, Woo Pyun, and Dim-Lee Kwong “Nickel nanocrystal formation on HfO2 dielectric for nonvolatile memory device applications”, Applied Physics Letters 86, 103505 (2005)
[1.34] Wei-Ren Chen, Ting-Chang Chang, Po-Tsun Liu, Po-Sun Lin, Chun-Hao Tu, and Chun-Yen Chang “Formation of stacked Ni silicide nanocrystals for nonvolatile memory application”, Applied Physics Letters 90, 112108 (2007)
[1.35] S. K. Samanta, Won Jong Yoo, and Ganesh Samudra, “Tungsten nanocrystals embedded in high-k materials for memory application”, Applied Physics Letters 87, 113110 (2005)
[1.36] S. K. Samanta, P. K. Singh, Won Jong Yoo, Ganesh Samudra, and Yee-Chia Yeo, “Enhancement of Memory Window in Short Channel Non-Volatile Memory Devices Using Double Layer Tungsten Nanocrystals”, IEEE (2005)
[1.37] Shan Tang, Chuanbin Mao, Yueran Liu, and Sanjay K. Banerjee “Protein-Mediated Nanocrystal Assembly for Flash Memory Fabrication”, IEEE Trans. on Electron Letters, vol. 54, no. 3, March 2007.
[1.38] L. Guo, E. Leobandung, and S. Y. Chou, “Si single-electron MOS memory with nanoscale floating-gate and narrow channel,” in Int. Electron Devices Meeting Tech. Dig., 1996, pp. 955–956.
[1.39] N. Takahashi, H. Ishikuro, and T. Hiramoto, “A directional current switch using silicon electron transistors controlled by charge injection into silicon nano-crystal floating dots,” in Int. Electron Devices Meeting Tech. Dig., 1999, pp. 371–374.
[1.40] J. Wahl, H. Silva, A. Gokirmak, A. Kumar, J. J. Welser, and S. Tiwari, “Write, erase and storage times in nanocrystal memories and the role of interface states,” in Int. Electron Devices Meeting Tech. Dig., 1999, pp. 375–378.
Chapter 2
[2.1] Chih-Yuan and Chin-Chieh Yeh, “Advenced Non-Volatile Memory Devices with Nano-Technology”, Invited Talk for 15th International Conference on Ion Implantation Technology, 2004.
[2.2] P. Pavan, R. Bez, P. Olivo, and E. Zanoni, Proceedings of The IEEE, 85, 1248 (1997)
[2.3] M. Woods, Nonvolatile Semiconductor Memories: Technologies, Design, and Application, C. Hu, Ed. New York: IEEE Press, (1991) ch. 3, p.59.
[2.4] T. Ohnakado, H. Onoda, O. Sakamoto, K. Hayashi, N. Nishioka, H. Takada, K. Sugahara, N. Ajika and S. Satoh, “Device characteristics of 0.35 �慆 P-channel DINOR flash memory using band-to-band tunneling-induced hot electron (BBHE) programming”, IEEE Trans. Electron Devices, Vol. 46, pp. 1866-1871, 1999.
[2.5] J. Bu, M. H. White, Solid-State Electronics., 45, 113 (2001)
[2.6] M. L. French, M. H. White., Solid-State Electron., p.1913 (1995)
[2.7] M. L. French, C. Y. Chen, H. Sathianathan, M. H. White., IEEE Trans Comp Pack and Manu Tech part A., 17, 390 (1994)
[2.8] Y. S. Hisamune, K. Kanamori, T. Kubota, Y. Suzuki, M. Tsukiji, E. Hasegawa, A. Ishitani, and T. Okazawa, IEDM Tech. Dig., p.19 (1993)
[2.9] Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, IEEE Transactions of
Electron Devices., 49, 1606 (2002)
[2.10] J. Moll, Physics of Semiconductors. New York: McGraw-Hill, (1964)
[2.11] M. Lezlinger and E. H. Snow, J. Appl. Phys., 40, 278 (1969)
[2.12] Christer Sevensson and Ingemar Lundstrom, J. Appl. Phys., 44, 4657 (1973)
[2.13] P. E. Cottrell, R. R. Troutman, and T. H. Ning, IEEE J. Solid-State Circuits, 14, 442 (1979)
[2.14] C. Hu, IEDM Tech. Dig., p.22. (1979)
[2.15] S. Tam, P. K. Ko, C. Hu, and R. Muller, IEEE Trans. Elec. Dev., 29, 1740 (1982)
[2.16] I. C. Chen, C. Kaya, and J. Paterson, IEDM Tech. Dig., p.263 (1989)
[2.17] I. C Chen, D. J. Coleman, and C. W. Teng, IEEE Elec. Dev. Lett., 10, 297 (1989)
[2.18] T. Ohnakado, K. Mitsunaga, M. Nunoshita, H. Onoda, K. Sakakibara, N. Tsuji, N. Ajika, M. Hatanaka and H. Miyoshi, IEDM Tech. Dig., p.279 (1995)
[2.19] Suk-Kang Sung, I1-Han Park, Chang Ju Lee, Yong Kyu Lee, Jong Duk Lee, Byung-Gook Park, Soo Doo Chae, and Chung Woo Kim, ”Fabrication and Program/Erase Characteristics of 30-nm SONOS Nonvolatile Memory Devices, ” IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL.2, NO.4, DECEMBER 2003.
[2.20] P. Pavan, R. Bez, P. Olivo, and E. Zanoni, Proceedings of The IEEE, 85, 1248 (1997)
[2.21] D. Ielmini, A. Spinelli, A. Lacaita, and A. Modelli, “Statistical model of reliability and scaling projections for Flash memories,” in IEDM Tech. Dig., 2001, pp.32.2.1–32.2.4.
[2.22] D. Ielmini, A. S. Spinelli, A. L. Lacaita, L. Confalonieri, and A. Visconti,“New
technique for fast characterization of SILC distribution in Flash arrays,” in Proc. IRPS, 2001, pp. 73–80.
[2.23] D. Ielmini, A. S. Spinelli, A. L. Lacaita, R. Leone, and A. Visconti, “Localization of SILC in Flash memories after program/erase cycling,” in Proc. IRPS, 2002, pp. 1–6.
[2.24] Y. M. Niquet, G. Allan, C. Delerue and M. Lannoo, “Quantum confinement in germanium nanocrystals,” Applied Physics Letters, vol.77, pp.1182-1184 (2000)
[2.25] T. Takagahara and K.Takeda, “Theory of the quantum confinement effect on excitons in quantum dots of indirect- gap materials,” Phys. Rev. B, Vol. 46, p. 15578, 1992.
[2.26] J.D.Jackson, “Classcial Electrodynamics”, published by John Wiley & Sons, 1999.
Chapter 3
[3.1]. D. Kahng and S. M. Sze, Bell Syst. Tech. J., 46, 1288 (1967).
[3.2]. J. De Blauwe, IEEE Trans. Nanotechnol., 1, 72 (2002).
[3.3]. S. Tiwari, F. Rana, K. Chan, H. Hanafi, C. Wei, and D. Buchanan, in International Electron Devices Meeting Technical Digest, p. 521 (1995).
[3.4]. Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, IEEE Trans. Electron Devices, 49, 1606 (2002).
[3.5]. F. M. Yang, T. C. Chang, P. T. Liu, P. H. Yeh, U. S. Chen, Y. C. Yu, J. Y. Lin, S. M. Sze, and J. C. Lou, Appl. Phys. Lett., 90, 212108 (2007).
[3.6]. W. R. Chen, T. C. Chang, P. T. Liu, P. S. Lin, C. H. Tu, and C.-Y. Chang, Appl. Phys. Lett., 90, 112108 _2007_.
[3.7]. T. Bing-Yue, W. Ming-Da, and G. Tian-Choy, IEEE Electron Device Lett., 22, 463 (2001).
[3.8]. T. C. Hsiao, P. Liu, and J. C. S. Woo, IEEE Electron Device Lett., _12, 126 (1996).
[3.9]. P. S. Lysaght, P. J. Chen, R. Bergmann, T. Messina, R. W. Murto, and H. R. Huff, J. Non-Cryst. Solids, 303, 54 (2002).
[3.10]. T. L. Li, W. L. Ho, H. B. Chen, H. C. H. Wang, C. Y. Chang, and C. Hu, IEEE Trans. Electron Devices, 53, 1420 (2006).
[3.11] T.I. Koranyi, et al., J. Catal. 116, 422 (1989).
Chapter 4
[4.1] Y. Yang, A. Purwar and M. H. White, “Reliability considerations in scaled SONOS nonvolatile memory devices”. Solid-State Electronics, Vol. 43, pp.2025-2032, 1999.
[4.2] C. H. Tu, T. C. Chang, P. T. Liu, H. C. Liu, S. M. Sze, C. Y. Chang, “Formation of germanium nanocrystals embedded in silicon-oxide-nitride layer”, Applied Physics Letters, Vol. 89, Art. No. 052112,
[4.3] T.I. Koranyi, et al., J. Catal. 116, 422 (1989).
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top