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研究生:林明澤
研究生(外文):Ming-Tze Lin
論文名稱:可設定式雙模低失真類比數位轉換器
論文名稱(外文):Configurable Dual-mode Low-distortion A/D Converter
指導教授:洪崇智
指導教授(外文):Chung-Chih Hung
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電信工程系所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2007
畢業學年度:96
語文別:英文
論文頁數:90
中文關鍵詞:雙模低失真前饋式音頻量測過取樣
外文關鍵詞:dual-modeincrementalsigma-deltafeedforwardlow-distortionoversampling
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隨著多功能裝置需求的快速成長,如手機、mp3播放器等,多功能在今日已經變得越來越重要。在今日的裝置應用,數位電路主導整個晶片的面積。無論如何,類比轉數位介面是不可少的。使用超取樣與雜訊型化的三角積分器調變器是非常有效的技術應用在高解析度類比數位轉換器上。它本身對原件不匹配與漂移非常不敏感,而這項特點非常適合今日的VLSI設計。考慮兩種三角積分調變器,應用在音頻的三角積分調變器與應用在量測的累加調變器, 他們擁有相似的架構,並且可以用共用或者整合的方式設計在一起。因此,這個可調式超取樣類比數位轉換器不僅可以擁有兩種功能,並且可以減少晶片面積。除此之外,多級或疊接調變器,也叫做MASH,在實現方面不會有穩定性的問題還可以更適合做設計上的控制。此外,向前饋入的架構更適合此種電路,讓它有低失真的效果。

因此,為了將兩種電路合併用低失真MASH的架構實現,這個研究重點放在如何設計可設定式雙模低失真類比數位轉換器。晶片是以台積電0.18微米標準互補式金氧半導體製程所製造。在音頻應用上使用過取樣率128,也就是操作頻率為5.12 MHz,量測結果是58 dB 動態輸入範圍和 55 dB訊號失真雜訊比。在量測應用上使用操作頻率5.12 MHz的量測結果與預測使用同樣的轉換時間相比低3 bit。這個論文證明此架構引導出一種簡單且模組化的架構。
With the rapid growth in demand for multi-function device such as cellular phone and MP3 player, multi-function has become more and more important today. In today’s device application, digital circuits dominate the whole chip function. However, the analog-to-digital converter (ADC) is indispensable. The Sigma-delta modulation, associated with oversampling and noise shaping, is a well-known technique used in high-accuracy A/D converters. It is almost insensitive to component matching and variation and is suitable for today’s VLSI design. Concerning the two sigma-delta modulators, the Sigma-delta modulator for audio application and incremental modulator for measurement, they have similar architectures and can be combined together by sharing or merging their similar parts. Therefore, this configurable oversampling A/D converter can not only have two functions but also reduce the chip area. Besides, multistage or cascade modulators, also called MASH, can be realized without stability problems and more programmable. In addition, feedforward configuration is suitable for this circuit to have low-distortion.

In order to combine the two circuits using feedforward MASH configuration, this research will focus on how to design a configurable dual-mode low-distortion A/D converter. The chip has been fabricated by TSMC 0.18-um CMOS process. With an oversampling ratio of 128 and a clock frequency of 5.12 MHz, the modulator achieves a 58 dB dynamic range and a peak SNDR of 55 dB for audio application. The measured resolution of the measurement application is 3 bit lower than the prediction in the same conversion time with a clock frequency of 5.12 MHz. This thesis demonstrates that this concept leads to a very simple modular architecture.
Chapter 1 Introduction..... 1
1.1 Motivation.... 1
1.2 Thesis Organization.... 2
Chapter 2 An Overview of Sigma-Delta Data Converters.. 4
2.1 Introduction.. 4
2.2 Overview of Analog-to-Digital Data Converters..... 4
2.2.1 Categories of Analog-to-Digital Data Converters. 4
2.2.2 Oversampling Ratio (OSR)...... 5
2.2.3 Signal to Noise Ratio (SNR)... 6
2.2.4 Signal to Noise and Distortion Ratio (SNDR)..... 6
2.2.5 Spurious Free Dynamic Range (SFDR)..... 7
2.2.6 Dynamic Range (DR)... 7
2.2.7 Effective Number of Bits (ENOB)........ 7
2.2.8 Overload Level (OL).. 7
2.3 Sampling Theorem....... 8
2.4 White Noise... 8
2.5 Oversampling Technique. 10
2.6 Noise Shaping Strategy. 13
2.6.1 First-Order Sigma-Delta Modulator...... 15
2.6.2 Second-Order Sigma-Delta Modulator..... 18
2.6.3 Higher-Order Sigma-Delta Modulator..... 21
2.6.4 Multi-Stage Sigma-Delta Modulator (MASH) (Cascaded)........ 23
2.6.5 System Analysis of Sigma-Delta Analog-to-Digital Converters........ 25
2.7 Digital Decimation Filter....... 27
2.8 Summary....... 30
Chapter 3 Basic Concept of Incremental ΔΣ Converters.. 31
3.1 Introduction.. 31
3.2 Theory and application of incremental ΔΣ converter 31
3.3 High-order incremental converters........ 34
3.4 Offset and charge injection compensation. 42
3.4.1 Conversion using analog error compensation...... 42
3.4.2 Conversion using analog error compensation...... 44
3.5 Summary....... 46
Chapter 4 Design of Configurable Dual-mode Low-distortion A/D Converter..... 47
4.1 Introduction.. 47
4.2 System consideration... 47
4.3 Behavior simulation.... 56
4.4 Circuit level implementation.... 60
4.4.1 Operational Amplifier 64
4.4.2 Comparator.. 67
4.4.3 Clock generator...... 69
4.4.4 Bootstrapped switches 70
4.5 Simulation result...... 72
4.6 Layout level design.... 75
Chapter 5 Test Setup and Experimental Results 77
5.1 Introduction.. 77
5.2 Measuring Environment.. 77
5.2.1 Power Supply Regulators....... 79
5.2.2 Input Terminal Circuit........ 80
5.3 Testing Board, and Pin Configuration..... 81
5.4 Performance Evaluations of Configurable Dual-mode Low-distortion A/D Converter... 82
5.5 Summary....... 86
Chapter 6 Conclusions...... 88
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