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研究生:吳歷恭
論文名稱:軟體無線電之無乘法器取樣率轉換器
論文名稱(外文):Multiplier-Less Sample Rate Conversion for Software Radio Terminals
指導教授:紀翔峰
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電信工程系所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
畢業學年度:96
語文別:英文
論文頁數:88
中文關鍵詞:軟體無線電取樣率取樣率轉換
外文關鍵詞:Software RadioSample Rate ConversionSRC
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軟體無線電(Software Radio)必須處理不同種類的通訊標準,這些標準可能使用不同的系統頻率(Master Clock Rate)。為了支援這些標準,比較合理的作法是讓類比轉數位(ADC)和數位轉類比(DAC)轉換器工作在固定的頻率,利用數位的作法改變取樣頻率以支援不同的通訊協定。轉換取樣率的理論是大家熟知的內插器(interpolator),該裝置可以用來計算取樣信號之間的數值。然而,即使已經有了內插器,內插出的信號可能和正確的信號點,有些微的時序偏差(timing offset)。換句話說,系統仍受限於內插器的解析度。傳統上我們會提高內插器的解析度來處理這個問題,這個方法會需要高階(order)的內插器以及多個乘法器。這篇論文將介紹一套無乘法器的取樣率轉換器。我們會建立取樣時間誤差(timing offset)的數學模型,並用他來解釋一個根本的問題:為什麼需要使用高解析度的內插器。根據這個模型,本論文提出的取樣率轉換器,將可以用較低解析度的內插器,達成較好的效能。最後我們會證明這個架構是簡單而且容易在硬體上實作。跟傳統的作法比起來,只需要些許的修改即可。
Software radio terminals must be able to process many various communication standards. These communication standards are based on different master clock rates. To support these clock rates, a reasonable solution is to clock the ADC and DAC at a fixed master clock rate and perform sample rate conversion (SRC) completely in digital domain. The underlying theory of SRC is well-studied interpolation filter which is used to calculate new samples at arbitrary time in between existing samples. However, even the interpolator is available; available intermediate signal points may not be exactly the desired ones where timing offset may exist. In other words, we are still limited by resolution of the interpolator. To deal the problem, the traditional method is to raise the time-domain resolution to meet the requirement. This way may need high order interpolator which requires multiple general purpose multipliers. In this thesis, a multiplier-free SRC architecture is proposed. We will build the mathematical model for timing jitter and use it to explain the elementary problem that why do we need to employ high resolution interpolator. Based on the model, the proposed SRC architecture could use low resolution interpolator but achieves better performance. Finally, we will show that the proposed SRC architecture is simple and easy to implement. As compared with the traditional approach, only minor modifications are needed.
摘要 I
Abstract II
Acknowledgement III
Contents IV
List of Figures VII
List of Tables IX
Chapter 1 Introduction 1
Chapter 2 SRC Overview 4
2.1 SRC Model 4
2.2 Traditional FIR Implementation SRC 6
2.3 Polynomial Based SRC 6
2.4 Timing Circuit for SRC 8
2.5 Summary 9
Chapter 3 Overview of Proposed Multiplier-less SRC Architecture 10
3.1 Overview of the Proposed SRC Architecture 10
3.2 Function Description 11
3.2.1 Clock scheduling 11
3.2.2 B-spline Interpolator 11
3.2.3 Fractional Factor Decimator 12
3.2.4 Integer factor decimator 12
3.3 System Parameter 12
3.3.1 System Parameter & Constrain 12
3.3.2 Case study: GPS Receiver 13
Chapter 4 B-spline Interpolation and Modified B-spline Interpolator 15
4.1 B-spline interpolation 15
4.1.1 Introduction 15
4.1.2 Continuous B-spline Basis Function 16
4.1.3 Derivative of Continuous B-spline Basis 17
4.1.4 Discrete B-spline Basis Function 18
4.1.5 Signal representation and Interpolation 20
4.1.6 Cardinal Splines 22
4.1.7 Multi-resolution Spline Processing 23
4.2 B-spline Interpolator Performance Analysis 26
4.2.1 Performance of B-spline Interpolation 26
4.2.2 Performance of Modified B-spline 28
4.3 Hardware implementation 29
4.3.1 Pre-filter 29
4.3.2 Parallel CIC-filter 32
4.4 Summary 34
Chapter 5 Mathematics Model for Fractional Factor Decimator 35
5.1 Introduction 35
5.2 B-spline Interpolation Revisit 36
5.3 System Model 37
5.4 Spectrally Shaped Sample-Time Residue 45
5.5 Summary 47
Chapter 6 Fractional Factor Decimator 48
6.1 Overview of Fractional Factor Decimator 48
6.2 Sigma-Delta Modulator 49
6.2.1 Delta Sigma Toolbox 51
6.2.2 Timing Jitter Simulation 54
6.2.3 Hardware Implementation and 2nd Order Sigma-Delta Modulator 59
6.2.4 1st Order Sigma-Delta Modulators 62
6.2.5 3rd Order Sigma-Delta Modulators 64
6.2.6 Performance Comparison of 1st and 2nd Order Sigma-Delta Modulators 64
6.3 Selector 66
6.4 Error Caused by Timing Jitter 66
6.4.1 PSD of Error Signal: error[n] 68
6.4.2 PSD of 1st Order Error Residue 68
6.4.3 PSD of 2nd Order Error Residue 70
6.4.4 PSD of Multiple Levels Sigma-Delta Modulator 71
6.4.5 PSD of Different Selector Configurations 72
6.4.6 Average and Worst SNR of Fractional Factor Decimator 74
6.5 Summary 77
Chapter 7 Integer Factor Decimator 78
7.1 Overview of Integer Factor Decimator 78
7.2 Sharpened CIC Filter 79
7.3 Half-Band Filter 81
7.4 Performance 83
7.5 Summary 84
Chapter 8 Conclusion 85
Bibliography 86
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