臺灣博碩士論文加值系統

和差調變器以往是非常廣泛的應用於低中頻寬、高解析度的一項技術。然而相較於過去傳統所常用的交換型電容(離散時間)的技術，隨著對於頻寬需求的增加，連續型的電路設計方式將會更適合於現今高頻寬的應用。本論文就實現連續型和差調變器來做一些探討。在於和差調變器回授路徑上，不同的延遲時間將會依據一些數學理論來做詳細地分析。此晶片使用台積電0.18μm CMOS 製程，供應電壓為1.8 V，消耗功率為6.5-mW，晶片核心面積為0.05mm2。模擬結果在100MHz的取樣頻率、2MHz 的頻寬內得到峰值SNDR為 62dB。

A ΔΣ modulator is well-known as a very efficient technique for the implementation of high resolution A/D converters in low to medium bandwidth applications. Comparing with switched-capacitor (discrete-time) technique in the past, the continuous time circuitry is more suitable for today’s growing bandwidth applications. The thesis presents the implementation of a ΔΣ modulator with continuous-time techniques. Different numbers of digital delay in the ΔΣ feedback loop have been analyzed based on mathematic theorems in detail. The chip is designed with 1.8V power supply by using 0.18μm TSMC CMOS process, with power consumption 6.5mW and the core area 0.05mm2. The simulation result shows that the ADC achieves a 62dB peak signal-to-noise pulse distortion ratio (Peak-SNDR) within a 2MHz bandwidth with a sampling rate of 100MHz

ABSTRACT I
ACKNOWLEDGMENTS III
CONTENTS IV
LIST OF TABLES VI
LIST OF FIGURES VI
CHAPTER 1 1
INTRODUCTION 1
1.1 CONTINUOUS-TIME ΣΔ MODULATORS 1
1.2 ORGANIZATION OF THE THESIS 3
CHAPTER 2 4
FUNDAMENTALS OF ΣΔ MODULATORS 4
2.1 SAMPLING AND QUANTIZATION 4
2.2 NYQUIST-RATE, OVERSAMPLING AND NOISE-SHAPING CONVERTERS 5
2.3 ΣΔ MODULATOR DESIGN ISSUES 6
2.3.1 Performance Increase in ΣΔ Modulators 6
2.3.2 Stability Constraints and Scaling 7
2.4 CT LOOP FILTER SYNTHESIS 8
2.4.1 Equivalence between DT and CT 8
2.4.2 Rectangular Feedback Signal 10
2.4.3 Decaying RC Feedback Signal 12
2.4.4 With an Additional Feedback Path 13
2.4.5 Design Examples 14
2.5 ARCHITECTURES AND IMPLICIT ANTI-ALIASING FEATURE 20
2.5.1 Feed-Forward (FF) and Feedback (FB) Architectures 20
2.5.2 Implicit Anti-Aliasing Feature 21
CHAPTER 3 24
NON-IDEALITIES IN CT ΣΔ MODULATORS 24
3.1 ERRORS OF THE FILTERS 24
3.1.1 Gain Errors 25
3.1.2 Finite DC-Gain 26
3.1.3 Finite Gain Bandwidth 27
3.1.4 Further Filter Non-Idealities 28
3.2 ERRORS OF THE FEEDBACK DAC 29
3.2.1 Excess Loop Delay 29
3.2.2 Clock Jitter 30
3.2.3 Jitter Noise Power Analysis 34
3.2.4 Jitter Noise Model 36
3.2.5 Further DAC Non-Idealities 38
3.3 ERRORS OF THE INTERNAL QUANTIZER 39
CHAPTER 4 40
ANALYSIS ON DIFFERENT LOOP DELAY COMPENSATION 40
4.1 EXCESS LOOP DELAY COMPENSATION 40
4.2 NOISE POWER GAIN (NPG) 42
4.2.1 Boundary of Noise Power Gain 43
4.2.2 NPG Values of Different Delay Compensation 44
4.3 POLE LOCATIONS OF NOISE TRANSFER FUNCTION 45
4.4 THIRD ORDER SIMULATION RESULTS 47
4.5 ANALYSIS AND SIMULATION RESULT OF OTHER HIGHER ORDER ΣΔ MODULATOR 49
CHAPTER 5 56
A PRACTICAL CIRCUIT IMPLEMENTATION 56
5.1 LOOP FILTER IMPLEMENTATION 56
5.1.1 Active-RC Filter 58
5.1.2 Bias Circuit 60
5.1.3 Two-Stage Operation Amplifier 61
5.2 TRI-LEVEL QUANTIZER AND DAC REALIZATION 63
5.3 CIRCUIT LEVEL SIMULATION RESULT 68
CHAPTER 6 72
CONCLUSION 72
REFERENCES 73

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