臺灣博碩士論文加值系統

這個論文研究全數位鎖相回路振盪器之研究.。如何增加頻寬,，增高解析度和降低抖動的影嚮是我們全篇論文的重點。我們的設計是一個寬頻的輸出，我們可以輸出的頻率從0.66~460 MHz，每一步可以改變2.16奈秒。這個設計是一個數位訊號轉換為時間的設計，我們用數位訊號改變輸出的頻寬。我們在這裡也用到 AOI 和 OAI 作為微調的元件，這個元件可以提供0.01皮秒(pico-seconds)的解析度。為了降低抖動，我們使用電流鏡來達成我們的目的。如同眾所周知的，電感、電阻和電容的效應將使瞬間的電流破壞電壓源的穩定度，也將使得輸出的訊號不停的抖動。電流鏡可以使我們的設計穩定電壓源，也使得輸出的訊號更好。我們這篇論文的重點就會在寬頻、高解析度及降低抖動上面。從一些模擬的實驗上就可以看出我們設計的效果。我們更將把這個設計做到晶片上面，從實際的晶片來驗證我們設計的效果。

The thesis is based on All-digital-Phase-Locked- Loops (ADPLL).. We will discuss wide band, cell-based digital controlled oscillator (DCO) in this thesis. In our design, there is a wide bandwidth DCO. The frequency is from 0.66~ 460MHz step by 2.16ns. It is designed by Digital-to-Time (DTC) scheme. We also use AOI and OAI as Fine-tune cells. The best resolution of this design is 0.01 pico-seconds. We use UMC 90nm standard cell AOI to get this performance. In another way, we put current mirror in DCO for reduction of bounce noise. That will effectively reduce jitter caused by ground bounce. The wide bandwidth DCO use DTC to do the internal count for different bandwidth. That is a double loops scheme. AOI cell is the standard cell for fine tune solution. When we change the control bits of AOI, it change the capacitance of additional capacitor. The resolution of 0.01 pico-seconds is a good performance for DCO design. The output jitter is another issue. When the design is working, the transient current will make a serious ground bounce. It is the major source of jitter. How to reduce the ground bounce and jitter is the important topic for DCO design. Here we use current mirror to reduce the ground bounce and make the clean signal.

Chapter 1 Introduction 1
1.1 Thesis Background 1
1.2 Thesis Motivation 2
1.3 Thesis Contribution 2
1.4 Thesis Organization 3

Chapter 2 Basic concept of DCO Implementations (DCO) 4
2.1 All-Digital-Phase-Locked-Loop (ADPLL) 4
2.2 The basic concept of Digital-Controlled Oscillator (DCO) 5
2.2.1 Coarse-tune unit 6
2.2.2 Fine-tune unit 7

Chapter 3 Proposed Digital-Controlled-Oscillator (DCO) and simulation result 9
3.1 Overview of the proposed Digital-Controlled Oscillator 9
3.2 The proposed DCO architecture 13
3.3 Cell-based Digital Controlled Oscillator 15
3.3.1 Digital to time converter (DCO) 15
3.3.2 Coarse-tune cell 18
3.3.3 Fine-tune cell 19
3.3.4 Performance comparison with other work 24
3.4 Current mirror for jitter reduction 24

Chapter 4 Discussion and Future Work 27
4.1 Discussion 27
4.2 Future work 27

Reference 29

[1] Pao-Lung Chen, Ching-Che Chung, Chen-Yi Lee” A portable digitally controlled oscillator using novel varactors” IEEE Trans. Circuits an Syst. II, Express Briefs, Volume 52, Issue, May 2005 Page(s):233-237
[2] A.P. Chandrakasan, S. Sheng, and Robert W. Brodersen, “Low-Power CMOS Digital Design, “IEEE Journal of Solid-State Circuits, Vol.27,No.4,pp.473-484, April, 1992.
[3] Anne-Johan Annema, Brarn Nauta, R van Langevelde, and H. Tuinhout,”Analog Circuits in Ultra-Deep-Submicron CMOS,”IEEE Journal of Solid-State Circuits, Vol. 40, No.1,pp.132-143, Jan.2005.
[4] J.Dunning,G.Garcia,J.Lundberg, and Ed Nuckolls,” An All-digital Phase-Locked Loop with 50-cycle Lock Time Suitable for High Performance Microprocessors” IEEE Journal of Solid-State Circuits, Vol. 30,No 4,pp.412-422,Apr.1995.
[5] Ching-Che Chung, Chen-Yi Lee, “An all-digital phase-locked loop for high-speed clock generation” IEEE Journal of Solid-State Circuits, Vol38,pp.347-351, Feb.2003
[6] Terng-Yin Hsu, Bai-Jue Shieh, and Chen-Yi Lee,” An All-Digital Phase-Locked Loop (ADPLL)-Based Clock Recovery Circuit” IEEE Journal of Solid-State Circuits, vol34,pp1063-1073, Aug. 1999
[7] Chia-Tsun Wu, Wei Wang, I-Chyn Wey, and An-Yeu Wu,” A Scalable DCO Design for Portable ADPLL Designs” Circuit and Systems, 2005, ISCAS 2005, IEEE International Symposium on 23-26 May 2005 Page(s):5449-5452 Vol.6
[8] Roth E, Thalmann M, Felber N, Fichtner W,” A delay-line based DCO for multimedia applications using digital standard cells only” Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.2003 IEEE International 2003 Page(s):432-505 Vol.1
[9] Abdollahi SR, Kiaei S, Bakkaloglu B, Fakhraie SM, Arivari R, Abdollahi SE,” An all-digital programmable digitally-controlled-oscillator(DCO) for digital wireledd applications” Circuits and Systems,2002. ISCAS 2002. IEEE International Symposium on Volume 4, 26-29 May 2002. Page(s):1V-101 –1V-104 Vol4.
[10] Olsson T, Nilsson P, “Portable digital clock generator for digital signal processing applications” Electronics Letters, Volume 39, Issue 19, 18 Sept.2003 Page(s):1372-1374.
[11] Terng-Yin Hsu, Bai-Jue Shieh, Chen-Yi Lee” An all-digital phase-locked loop(ADPLL)-based clock recovery circuit” Solid-State Circuits, IEEE Journal of Volume 34, Issue 8, Aug. 1999 Page(s):1063-1073.
[12] Terng-Yin Hsu, Chung-Cheng Wang, Chen-Yi Lee” Design and analysis of a portable high-speed clock generator” Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on. Volume 48,Issue4, April 2001 Page(s): 367-375.
[13] Olsson T, Nilsson P,” A digitally controlled PLL for SoC applications” Solid-State Circuits, IEEE Journal of Volume 39, Issue 5 May 2004 Page(s): 751-760.
[14] Guang-Kaai Dehng, June-Ming Hsu, Ching-Yuan Yang, Shen-Iuan Liu, “Clock-deskew buffer using a SAR-controlled delay-locked loop” Solid-State Circuits, IEEE Journal of Volume 35, Issue 8, Aug. 2000 Page(s):1128-1136.
[15] Jen-Shiun Chiang, Kuang-Yuan Chen, ”A 3.3V all digital phase-locked loop with small DCO hardware and fast phase lock” Circuits and Systems, 1998. ISCAS `98. Proceedings of the 1998 IEEE International Symposium on Volume 3, 31 May-3 June 1998 Page(s):554-557 Vol3.
[16] Jen-Shiun Chiang, Kuang-Yuan Chen, “The design of an all-digital phase-locked loop with small DCO hardware and fast phase lock” Circuit and System II: Analog and Digital Signal Processing, IEEE Transactions on Volume 46, Issue7, July 1999 Page(s):945-950.
[17] Yong Shim, Youngkwon Jo, Soohwan Kim, Kwangiun Cho” A register controlled delay locked loop using a TDC and a new fine delay line scheme” Cricuits and Systems, 2006 ISCAS 2006. Proceedings, 2006 IEEE International Symposium on 21-24 May 2006
[18] Garlepp B.W, Donnely K.S, Jun Kim,”A portable digital DLL for high-speed CMOS interface circuits” Solid-State Circuits, IEEE Journal of Volume 34, Issue 5, May 1999 Page(s):632-644.
[19] Garlepp, B.W, Donnely K.S, Jun Kim,”A portable digital DLL architecture for CMOS interface circuits” VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on 11-13 June 1998 Page(s)214-215.
[20] Raha,P; Randall, S; Jennings, R; Helmick, B; Amerasekera, A; Haroun, B;” A robust digital delay line architecture in a 0.13/spl mu/m CMOS technology node for reduced design and process sensitivities” Quality Electronic Design,2002. Proceedings. International Symposium on 18-21 March 2002 Page(s):148-153.