由於近來行動通訊品質的提高，通訊頻寬的需求量大增，衍生而出許多的通訊規格，例如：GPRS、3G、Bluetooth、802.11n…等，且於終端的使用者對於產品之輕、薄、短、小、久(產品可靠度)的要求越來越重視，所以使射頻積體電路封裝技術的挑戰越來越大。封裝對元件的功能主要在於傳遞電源能量及電路訊號、保護元件結構、提供散熱管道，其中又以電能、電訊的傳輸為射頻積體電路相當重要的考量。由於射頻電路工作頻率相當高，其原有的低頻電路特性則因頻率的增加而有所改變，以簡單的單一導線為例，原為傳輸訊號導通與不導通的判定，隨著工作頻率的提升其寄生電感(Parasitic Inductance)、肌膚效應(Skin Effect)及寄生電阻(Parasitic Resistance) …等現象。但是利用覆晶的方式連結射頻積體電路與基板，其覆晶接合封裝的單晶微波積體電路與裸晶的電性表現幾乎相同，固有許多研究單位投入覆晶封裝技術。
本論文研究方向是針對Gold-to-Gold之覆晶封裝高頻元件，做高頻特性、可靠度及機械強度之試驗，並且分析各種不同條件下，特性之變化。

As the proliferation of high-quality mobile communication increased recently, the demand of large bandwidth of communication increased recently, too. As a result, several communication specifications was developed, such as GPRS、3G、Bluetooth、802.11n…etc. Furthermore, miniature and durable portable products are more and more valued by ender users. The challenge of high frequency package is more and more tough. The main functions of package are Power Distribution、Signal Distribution、Protection and Heat Dissipation. The most important function of them is Signal Distribution. Due to the high work frequency of high frequency device, the alterations of frequency have modified the characteristic of normal device. The statuses including Parasitical Inductance、Skin Effect、Parasitical Resistance are different in different working frequency devices. With the application of utilizing the Flip-Chip package to connect the high frequency device and substrate, this joint development represents the almost same result of Power Distribution in SOT and Die. Therefore, the result attracts a lot of research units to develop and study the tech of Flip-Chip package.
The thesis directions are to test the Gold-to-Gold Flip-Chip package of high frequency devices in the first section. The tests include high frequency property、reliability、and mechanical test. In the second section, are to analyze the variations of property in different conditions.

中文摘要………………………………………………………………Ⅰ
英文摘要………………………………………………………………Ⅲ
誌謝……………………………………………………………………Ⅴ
目錄……………………………………………………………………Ⅵ
表目錄…………………………………………………………………Ⅷ
圖目錄…………………………………………………………………Ⅸ
一、緒論………………………………………………………………1
1.1前言…………………………………………………………………1
1.2研究動機與目的……………………………………………………2
二、Introduction………………………………………………………3
2.1 Chip-level interconnect techniques…………………………3
2.1.1 打線接合(Wire bonding)…………………………………4
2.1.2 覆晶(Flip chip)…………………………………………6
2.2 Interconnections in flip-chip packaging system…………9
2.2.1 錫鉛凸塊(Solder bumps)…………………………………9
2.2.2 異方性導電膠膜(ACF)……………………………………11
2.2.3 金凸塊(Gold-to-Gold bumps)…………………………13
2.3 可靠度概論………………………………………………………15
2.3.1 瞬間故障曲線……………………………………………15
2.3.2 可靠度測試方法…………………………………………16
三、實驗步驟與分析分法……………………………………………19
3.1 實驗步驟及試片準備……………………………………………19
3.1.1 Substrate gold circuits and gold bumps …………20
3.1.2 Chip gold circuits……………………………………22
3.1.3 Flip-chip assembly……………………………………23
3.1.4 Underfilling……………………………………………25
3.2 Mechanical and reliability tests…………………………26
3.2.1 Shear force test………………………………………26
3.2.2 Thermal cycling test…………………………………28
3.2.3 吸濕測試…………………………………………………29
3.2.4 爆米花測試(Popcorn test)……………………………30
3.2.5 Electric resistance measurement…………………32
3.2.6 RF measurement…………………………………………33
四、實驗結果討論……………………………………………………35
五、結論………………………………………………………………46
六、參考文獻…………………………………………………………48

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