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研究生:張譽繽
研究生(外文):Yu-Bin Chang
論文名稱:一種應用於NAND型快閃記憶體之基於抹除碼的平行化技術
論文名稱(外文):An Erasure-code-based Striping Scheme for NAND-Flash Storage System
指導教授:張立平張立平引用關係
指導教授(外文):Li-Pin Chang
學位類別:碩士
校院名稱:國立交通大學
系所名稱:網路工程研究所
學門:電算機學門
學類:網路學類
論文種類:學術論文
論文出版年:2007
畢業學年度:96
語文別:英文
論文頁數:17
中文關鍵詞:快閃記憶體儲存系統入式系統作業系統
外文關鍵詞:Flash memorystorage systemsembedded systemsoperating systems
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在一塊大塊的快閃記憶體中,使用多重小塊的快閃記憶體(bank)做平行化存取,主要是用來提高系統存取時的效能,此種做法已經很普遍了,然而,現實環境中的資料存取,將使得各個bank 間存取工作量的不平均,如此導致平行化存取產生的效能被限制住,在這篇研究中,我們將比較常存取的資料作編碼成另一份資料,這類資料也就是消除碼(erasure codes),因為消除碼只要與部份的原始資料一起做解碼後,即可回復原本的資料,而一份要求中含很多的小型工作,研究的目的是希望能將小型工作從工作量重的bank 中,藉由其餘工作量輕的bank 中的消除碼取代,如此達到bank間工作量的平衡,研究中主要討論分成(1)如何製作與分派消除碼(2)如何放置消除碼於bank 中(3)消除碼分派與放置完後,一份要求來後該如何的做排班。由實驗結果,我們發現只要提供10%的額外空間作消除碼,即可使得
讀取的動作提高了50%的效能。
To use multiple memory banks in parallel is a nature approach to boost the performance of flash-memory storage systems. However, realistic data-access localities unevenly load each memory bank and thus the benefits of parallelism
is severely limited. In this work, we propose to encode popular data with redundancy by means of erasure codes. Load balancing is thus achieved by accessing only lightly loaded banks, because to retrieve a subset of data blocks
and code blocks sufficiently reconstructs the requested data. The technical issues pertain to redundancy allocation, redundancy placement, and request scheduling.
By experiments, we found that, by offering 10% extra redundant space, the read response time is largely improved by 50%.
中文提要 ……………………………………………………………… i
英文提要 ……………………………………………………………… ii
誌謝 ………………………………………………………………… iii
目錄 ………………………………………………………………… iv
表目錄 ………………………………………………………………… v
圖目錄 ………………………………………………………………… vi
一、 Introduction…………………………………………………… 1
二、 System Model and Problem Formulation…………………… 3
2.1 A Striping System……………………………………………… 3
2.2 Localities of Reads and Writes……………………………… 4
三、 An Erasure-Code-Based Striping Scheme ………………… 5
3.1 Redundancy Allocation and Placement ……………………… 5
3.2 Request Scheduling …………………………………………… 6
3.3 A Read-ahead Policy…………………………………………… 8
四、 Experimental Results ………………………………………… 9
4.1 Experimental Setup and Performance Metrics……………… 9
4.2 Numerical Results……………………………………………… 10
4.2.1 Number of Code Zones……………………………………… 10
4.2.2 Stripe-Block Sizes………………………………………… 11
4.2.3 Zone Sizes…………………………………………………… 12
4.3 Discussions …………………………………………………… 12
五、 Conclusion…………………………………………………………… 13
參考文獻 ……………………………………………………………… 13
附錄 ………………………………………………………………… 15
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