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研究生:簡佩怡
研究生(外文):Pei-yi Jian
論文名稱:應用於2.5GHz鎖相迴路之內建抖動量測電路
論文名稱(外文):Built-In Jitter Measurement Circuit for 2.5GHz Phase-Locked Loop
指導教授:鄭國興鄭國興引用關係
指導教授(外文):Kuo-Hsing Cheng
學位類別:碩士
校院名稱:國立中央大學
系所名稱:電機工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2007
畢業學年度:96
語文別:中文
論文頁數:64
中文關鍵詞:游標尺延遲線抖動量測內建自我測試
外文關鍵詞:vernier delay linejitter measurementbuilt-in self test
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隨著半導體製程之進步,積體電路發展已驅向系統單晶片化。當系統整合於同一晶片時即需要準確的時脈訊號,通常會選用鎖相迴路來當做參考時脈來源。因此鎖相迴路是單晶片系統中重要同步單位,而其時脈之抖動特性即為其重要效能。以往測試鎖相迴路效能多用外部儀器來做時脈抖動量測,但是今日因鎖相迴路操作頻率之提升,測試儀器成本大大提高。此外利用儀器量測時外部雜訊亦會干擾測試結果,因此產生了內建時脈抖動量測電路。
本論文提出的內建時脈抖動量測電路以減少測試時間、晶片面積及降低雜訊影響為設計目標。我們以游標尺延遲線電路加上自我取樣方法來實現時脈抖動量測電路。電路分為二級,首先由一週期延遲電路將時脈訊號快速延遲一週期,接著利用抖動量測電路做抖動量測。加上一週期延遲電路後即不再需要參考時脈,量測結果可不受參考時脈雜訊影響,並且能減少電路硬體消耗及加快測試時間。
此時脈抖動量測電路是利用聯電90奈米製程,完成一應用於2.5GHz鎖相迴路之內建時脈抖動量測電路,電路解析度為5.3ps。
As the improvement of semiconductor technology, System-On-Chip(SOC) is the current trend of VLSI circuit. When many systems were integrated into a chip, the reference clock signal must be accurate. We usually choose Phase-Locked Loop(PLL) circuit as the reference clock source. Since PLL is the essential synchronization element in SOC, the jitter characteristic is the most important property. In the past, the jitter was measured by the external equipment. But with the increase of PLL operating frequency, the cost of test equipment has greatly raised. Besides, the external equipment may induce noise, so the built-in self test circuit is proposed.
The design purpose of this thesis is designing a built-in self test circuit with less test time, smaller chip area and lower power noise effect. We use vernier delay line circuit with self-sample method to accomplish this work. The circuit is composed of two stages. The first stage is one period delay circuit. It can delay input clock signal one period rapidly. The second stage is jitter measurement circuit. It has high resolution when measuring jitter. With the one period delay circuit, the measurement result will not be affected by the reference clock noise, reduce some chip area and speed up the test time
This built-in self test circuit for 2.5GHz PLL is implemented in UMC 90nm CMOS technology, the circuit resolution is 5.3ps.
摘 要 i
Abstract ii
目錄 iii
圖目錄 v
表目錄 vii
第一章 緒論 1
1.1 研究動機 1
1.2 論文架構 2
第二章 時脈抖動定義 3
2.1 時脈抖動的定義(Jitter Definition) 3
2.1.1 週期對週期時脈抖動(JCC) 3
2.1.2 週期時脈抖動(JPER) 4
2.1.3 長期的時脈抖動(JLONG) 5
2.2 時脈抖動分佈圖(Jitter Histogram) 6
第三章 時脈抖動量測方法文獻回顧 8
3.1 傳統Off-Chip時脈抖動量測方法 8
3.2 On-Chip時脈抖動量測 9
3.3 On-Chip時脈抖動量測相關研究 9
3.3.1 時間數位轉換器(Time-to-Digital Converter)[8] 10
3.3.2 延遲串列方法(Delay Chain Method) 11
3.3.3 游標尺延遲線方法(Vernier Delay Line Method)[10] 13
3.3.4 改良式游標尺延遲線方法 15
3.3.5 游標尺振盪器方法(Vernier Ring Oscillator Method)[6] 15
3.3.6 數位時脈抖動量測方法之比較 17
第四章 改良式鎖相迴路內建自我測試電路 18
4.1 自我取樣方法 18
4.2 改良式時脈抖動量測電路架構圖 19
4.3 改良式時脈抖動量測電路規格訂定 20
4.4 改良式時脈抖動量測電路子電路 23
4.4.1 相位偵測電路 23
4.4.2 一週期延遲產生電路 24
4.4.3 抖動量測電路 25
4.4.4 控制訊號產生器電路 28
4.4.5 計數器電路 28
4.4.6 振盪器電路 30
4.5 改良式時脈抖動量測電路全電路操作 31
4.5.1 校正模式(Calibration Mode) 32
4.5.2 量測模式(Measurement Mode) 33
4.5.3 量測時間 34
第五章 晶片實現與模擬 36
5.1 相位偵測電路 36
5.2 一週期延遲電路延遲元件 38
5.3 一週期延遲電路 40
5.4 抖動量測電路延遲元件 41
5.5 抖動量測電路 42
5.6 控制訊號產生器電路 44
5.7 計數器電路 45
5.8 全電路模擬 46
5.8.1 全電路佈局 46
5.8.2 校正模式模擬 48
5.8.3 量測模式模擬 49
5.8.4 電路規格與比較表 51
第六章 結論 52
6.1 結論 52
6.2 未來改進方向 52
參考文獻 54
[1]T. Okayasu, M. Suda, and K. Yamamoto, “CMOS Circuit Technology for Precise GHz Timing Generator,” Proc. of Int. Test Conf., pp. 894-902, 2002
[2]C.C. Tsai, “On-Chip Jitter Measurement for Phase-Locked Loop,” MS. Thesis, National Chiao Tung University, Institute of Electronics Engineering, Taiwan, 2002.
[3]F. Azais, M. Renovell, Y. Bertrand, A. Ivanova, and S. Tabatabaei, “A Unified Digital Test Technique for PLLs: Catastrophic Faults Covered,” Proc. of Int. Mixed Signal Testing Workshop, pp. 269-292, June 1999.
[4]K. A. Taylor, B. Nelson, A. Chong, H. Lin, E. Chan, M. Soma, “Special Issue on BIT CMOS Built-In Test Architecture for High-Speed Jitter Measurement,” IEEE Trans. on Instrumentation and Measurement, VOL. 54, NO. 3, pp.975-987, June 2005
[5]Nelson Soo, “Jitter Measurement Techniques,” Pericom Application Brief AB36, Nov.2000.
[6]A. H. Chan and G.W. Roberts, “A Synthesizable, Fast and High-Resolution Timing Measurement Device Using a Component-Invariant Vernier Delay Line” Proc. of Int. Test Conf., pp. 858-867, Nov 2001.
[7]Bozena Kaminska, “BIST Means More Measurement Options for Designers,” EDN Magazine, Dec. 2000.
[8]T Xia, J. C. Lo, “Time-to-Voltage Converter for On-Chip Jitter Measurement,” IEEE Trans. on Instrumentation and Measurement, Vol.52, pp. 1738-1748, Dec. 2003.
[9]S. Stephen and R. Audin, “BIST for Phase-Locked Loops in Digital Applications” Proc. of Int. Test Conf., pp. 532-540, Sep 1999.
[10]P. Dudek, S. Szczepanski, and J. Hatfield, “A High-Resolution CMOS Time-to-Digital Converter Utilizing a Vernier Delay Line,” IEEE J. Solid-State Circuits, vol. 35, pp. 240-247, Feb. 2000.
[11]K. H. Cheng, C. W. Huang and S. Y. Jiang, “Self-Sampled Vernier Delay Line for Built-in Clock Jitter Measurement,” IEEE International Symposium on Circuits and Systems, ISCAS, pp. 1591-1594, May 2006
[12]T. Xia, H. Zheng, J. Li, A. Ginawi, "Self-Refereed On-Chip Jitter Measurement Circuit Using Vernier Oscillators," isvlsi, pp. 218-223, 2005.
[13]S. Sunter, A. Roy, “On-Chip Digital Jitter Measurement, from Megahertz to Gigahertz,” IEEE, Design & Test of Computers, pp. 314-321, July 2004
[14]B. Nikolai, V. G. Oldobdzija, V. Stojanovic, W. Jia, J. K. Chiu and M. Mi. Leung, “Improved Sense-Amplifier-Based Flip-Flop: Design and Measurements,” IEEE Journal of Solid-State Circuits, vol. 35, pp. 876 -884, Jun 2000
[15]M. Mansuri, C. K. Yang, “A Low-Power Adaptive Bandwidth PLL and Clock Buffer With Supply-Noise Compensation,” IEEE Journal of Solid-State Circuits, vol. 38, NO. 11, November 2003
[16]A. H. Chan and G. W. Roberts, “A Jitter Characterization System Using a Component-Invariant Vernier Delay Line,” VLSI Systems, IEEE Transactions on Volume 12, Issue 1, pp.79-95 , Jan. 2004
[17]S. Tabatabaei and A. Ivanov, “Embedded timing analysis: A SoC infrastructure” IEEE Design & Test of Computers, vol. 19, pp. 22-34, May-June 2002.
[18]R. B. Staszewski, S. Vemulapalli, P. Vallur, J. Wallberg, and P. T. Balsara, “1.3 V 20 ps Time-to-Digital Converter for Frequency Synthesis in 90-nm CMOS,” IEEE Trans. on Circuits and Systems, vol. 53, NO. 3, March 2006
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