臺灣博碩士論文加值系統

隨著無線通訊普遍的發展，正交分頻多工(OFDM)和分離複頻(DMT)這類的多載波調變技術更進一步的重視其研究。舉例來說，地面/手持式數位影像傳輸(DVB-T/H)、數位音訊傳輸(DAB)、非對稱式數位電話線(ADSL)、高速數位電話線(VDSL)、電力線橋接器(PLC)等…。在OFDM系統中，多載波調變技術是將其分解成多個子載波做平行處理。於是，快速傅利葉轉換(FFT)和逆向快速傅利葉轉換(IFFT)在OFDM系統中是重要且運算複雜的部分。所以，如何減少運算時功率的消耗和硬體面積便是我們所要考量的。
此篇論文提出一個低功率混合基數(LPMR)之快速傅利葉轉換處理器，其使用基數為4/2(radix-4/2)為理論基礎並且以單埠記憶體存取方式實現快速傅利葉之運算，藉此來達到低功率之功效。此外，改善記憶體存取方式可以降低ROM之切換頻度而且可以縮短其運算時間。LPMR快速傅利葉轉換處理器需要兩組單埠記憶體，其中每一組長度有N個位址，而且利用基數為4當作其基本運算單元，可以同時處理一組基數為4或是兩組基數為2之基本運算。以運算1024點LPMR快速傅利葉轉換處理器而言，需要1280個運算周期，但是其輸出率只需1216個運算周期，即可將資料輸出。LPMR快速傅利葉轉換處理器是採用TSMC 0.18μm 製程，並且適用於2/4/8K點快速傅利葉轉換之運算，利用工作站電路合成至50MHz。並在20MHz和45MNz測量其功率消耗，分別做8192點之快速傅利葉轉換，其個別可分為23.85mW和 54.2mW。此外，LPMR之合成面積為2,325,656μm2。由以上觀察，和其他文獻相比之中，LPMR快速傅利葉轉換處理器可以更進一步地降低功率消耗。

As wireless communication popular development, multicarrier modulation techniques such as Orthogonal Frequency Division Multiplex (OFDM) and Discrete Multitone (DMT) have been placed importance on research further. For example, Digital Video Broadcasting-Terrestrial/Handheld (DVB-T/H), Digital Audio Broadcasting (DAB), Asymmetric Digital Subscriber Line (ADSL), Very-high-speed Digital Subscriber Line (VDSL), Powerline Communications (PLC), etc. Multicarrier modulation in OFDM system is realized by multi-subcarrier parallel operation. Consequently, Fast Fourier Transform (FFT) and Inverse Fast Fourier Transform (IFFT) are the most part and complicated computation in OFDM system. So how to reduce the operation power and minimize the FFT hardware cost become more momentous.
The paper proposes a new Low Power Mixed-Radix (LPMR) Fast Fourier Transform (FFT) processor. It uses radix-4/2 algorithm and performs single-port memory to access data in order to reduce power consumption. In addition, the improved in-place strategy for the Mixed-Radix (MR) algorithm can decrease the number of times for ROM transition and make the latency shorten. The LPMR FFT processor requires only two N-words single-port memories. Its architecture only has one radix-4 butterfly unit which can perform one radix-4 butterfly or two radix-2 butterflies at one clock cycle. The computation cycles between the first to the last operation and the latency between the first input to the first output for 1024-point operation of LPMR FFT are 1280 and 1216 clock cycles, respectively. The LPMR FFT processor uses TSMC 0.18μm cell library for 2/4/8K-point operation and runs at 50MHz. The power consumption of the 8192-point LPMR FFT processor operating at 20MHz and 45MHz are 23.85mW and 54.2mW, respectively. Besides, the area of 2/4/8K-point LPMR FFT processor is 2,365,656μm2. Therefore, the architecture of the LPMR FFT processor can further reduce power consumption and area comparing to the existing FFT processors on literatures.

第一章 前言………………………………………………………..........1
第二章 DVB-T 系統簡介...……………………..……......…….....2
2.1 分頻多工FDM 與正交分頻多工OFDM 之差異 ................................. 2
2.2 DVB-T 系統與規格 ................................................................................ 3
第三章 快速傅利葉轉換(FFT)理論……................................................6
3.1 基數為2 之快速傅利葉轉換(Radix-2 FFT)理論 .................................. 6
3.1.1 離散時間快速傅利葉轉換(DFT)理論 ................................................... 6
3.1.2 從頻域角度拆解基數為2 之離散快速傅利葉轉換(DIF) .................... 7
3.1.3 從時域角度拆解基數為2 之離散快速傅利葉轉換(DIT) .................... 9
3.2 基數為4 之快速傅利葉轉換(Radix-4 FFT)理論 ................................ 10
3.3 基數為22 之快速傅利葉轉換(Radix-22 FFT)理論 .............................. 13
3.4 基數為8 之快速傅利葉轉換(Radix-8 FFT)理論 ................................ 14
3.5 基數為23 之快速傅利葉轉換(Radix-23 FFT)理論………..………….17
3.6 基數為16、基數為32 快速傅利葉轉換(Radix-16、Radix-32 FFT)理論.18
3.7 分裂基數2/4、分裂基數2/8 快速傅利葉轉換(Split-Radix 2/4、Split-Radix 2/8 FFT)理論.18
第四章 管線式和記憶體式架構之快速傅利葉轉換……..……...…..21
4.1 單一回授路徑(SDF)快速傅利葉轉換架構設計 ................................. 21
4.1.1 基數為2 之SDF 架構運算 .................................................................. 21
4.1.2 基數為4 之SDF 架構運算 .................................................................. 22
4.1.3 基數為22 之SDF 架構運算 ................................................................. 23
4.1.4 基數為8 之SDF 架構運算 .................................................................. 24
4.1.5 基數為23 之SDF 架構運算 ................................................................. 25
4.1.6 SDF 架構各式FFT 運算總結……..…………………………...……..25
4.2 多重路徑交換器(MDC)快速傅利葉轉換架構設計……...…………..27
4.2.1 基數為2 之MDC 架構運算……………………………...…………..27
4.2.2 基數為4 之MDC 架構運算……………………………...…………..28
4.2.3 基數為22 之MDC 架構運算……………………………...………… 29
4.2.4 基數為8 之MDC 架構運算……………………………...…………..29
4.2.5 基數為23 之MDC 架構運算……………………………...…………..30
4.2.5 MDC 架構各式FFT 運算總結….……………………………...……..30
4.3 記憶體式快速傅利葉轉換架構設計………..…………….…………..32
4.3.1 TSMC CL018G製程技術….…………..……....……………….……..32
4.3.1.a 高速雙埠同步SRAM(RA2SH)...........................................…….……..32
4.3.1.b 高速雙埠同步Register File(RF2SH).…………………………..……..33
4.3.1.c 高速單埠同步SRAM(RA1SH)...………………………………….…..33
4.3.1.d 高速單埠同步Register File(RF1SH)…………………………….……34
4.3.2 各種記憶體式快速傅利葉架構設計…………………………………35
4.3.2.a 適用於DMT/OFDM 應用之記憶體式快速傅利葉轉換處理器[9]…..35
4.3.2.b 適用於VDSL 收發機之記憶體式快速傅利葉轉換處理器[10]………..37
4.3.2.c 高效能架構之記憶體式快速傅利葉轉換[11]………………………..…...38
4.3.2.d 使用新穎存取策略之連續流動混合基數快速傅利葉轉換處理器[12]…...39
4.3.3 記憶體式架構各式FFT 運算總結..…………………………………43
第五章 單埠記憶體式順序輸出(LSOM)快速傅利葉轉換處理器……...…….44
5.1 LSOM 快速傅利葉轉換處理器架構 ................................................... 44
5.2 LSOM 控制電路 ................................................................................... 48
5.2.1 LSOM 之記憶體控制電路 ................................................................... 48
5.2.2 LSOM 之組合邏輯元件控制電路 ....................................................... 52
5.2.3 LSOM 之ROM 控制電路 .................................................................... 54
5.3 記憶體式FFT 運算電路分析與比較 ................................................... 55
第六章 適用於DVB-T/H 系統之低功率混合基數(LPMR)單埠記憶體式快速傅
利葉轉換處理器…………………………………………..…….....…58
6.1 LPMR快速傅利葉轉換處理器架構….…………………………..…..58
6.2 LPMR控制電路…………………….……………………………..…..63
6.2.1 LPMR 之記憶體控制電路.………....……………………………..…..63
6.2.2 LPMR 之組合邏輯元件控制電路……...…..……………………..…..67
6.3 管線式和記憶體式之FFT 運算架構比較.………………………..…..70
6.4 LPMR 之DVB-T/H 系統應用…….......…..……………………..…..73
第七章 硬體實作與模擬結果..................................................................76
7.1 浮點模擬與定點運算……….….........…..……………………..…..76
7.2 FPGA 之模擬結果…….……….…........…..……………………..…..78
7.3 PrimePower 模擬LPMR之功率….…......…..……………………..…..80
第八章 結論與展望...................................................................84
參考文獻……….……………………………………………………….86

[1]E. Bidet, D. Castelain, C. Joanblanq, and P. Senn, ”A fast single-chip implementation of 8192 complex point FFT”, IEEE Journal of Solid-State Circuits, pp. 300-305, March 1995.
[2]M. Hasan, T. Arslan, and J.S. Thompson, ”A novel coefficient ordering based low power pipelined radix-4 FFT processor for wireless LAN applications”, IEEE Tran. on Consumer Electronics, pp.128-134, Feb. 2003.
[3]C.-C. Wang, J.-M. Huang, and H.-C. Cheng, ”A 2K/8K mode small-area FFT processor for OFDM demodulation of DVB-T receivers”, IEEE Trans. on Consumer Electronics, vol. 51, no. 1, pp.28-32, Feb. 2005.
[4]L. Yang, K. Zhang, H. Liu, J. Huang, and S. Huang, ”An efficient locally pipelined FFT processor”, IEEE Tran. on Circuits and Systems II: Express Briefs, vol. 53, no. 7, pp.585 – 589, July 2006.
[5]S.-C. Moon and I.-C. Park, ”Area-efficient memory-based architecture for FFT processing”, in Proc. Int. Symposium on Circuit and Systems (ISCAS), May 2003, pp. V101 - V104.
[6]L. Jia, Y. Gao, and H. Tenhunen, ”Efficient VLSI implementation of radix-8 FFT algorithm”, in Proc. IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, Aug. 1999, pp.468 – 471.
[7]S.-Y. Lee, C.-C. Chen, C.-C Lee, and C.-J. Cheng,” A low-power VLSI architecture for a shared-memory FFT processor with a mixed-radix algorithm and a simple memory control scheme”, in Proc. IEEE Int. Symposium on Circuits and Systems (ISCAS), May 2006, pp.157 – 160.
[8]Y. Zhao, A.T. Erdogan, and T. Arslan, ”A novel low-power reconfigurable FFT processor”, in Proc. IEEE Int. Symposium on Circuits and Systems (ISCAS), May 2005, pp.41 – 44.
[9]C.-H. Chang, C.-L. Wang, and Y.-T. Chang, “A novel memory-based FFT processor for DMT/OFDM applications”, in Proc. IEEE Int. Conf. on Acoustics, Speech, Signal Processing, March 1999, pp. 3206-3216.
[10]C.-L. Wang and C.-H. Chang, “A new memory-based FFT processor for VDSL transceivers”, in Proc. IEEE International Symposium on Circuits and Systems, May 2001, pp. 670-673
[11]C.-K. Chang, C.-P. Hung, and S.-G. Chen, “An efficient memory-based FFT architecture”, in Proc. Int. Symposium on Circuit and Systems (ISCAS), May 2003, pp. II-129 - II-132.
[12]B. G. Jo and M. H. Sunwoo, ”New continuous-flow mixed-radix (CFMR) FFT processor using novel in-place strategy”, IEEE Tran. on Circuits and Systems I: Regular Papers, vol. 52, no. 5, pp.911 – 919, May 2005.
[13]H. Jiang, H. Luo, J. Tian, and W. Song, ”Design of an efficient FFT Processor for OFDM systems”, IEEE Tran. on Consumer Electronics, vol. 51, no. 4, pp.1099 – 1103, Nov. 2005.
[14]Y. Zhao, A.T. Erdogan, and T. Arslan, ”A low-power and domain-specific reconfigurable FFT fabric for system-on-chip applications”, in Proc. 19th IEEE Int. Parallel and Distributed Processing Symposium, April 2005, pp.4.
[15]C.-H. Chang, C.-L. Wang, and Y.-T. Chang, “Efficient VLSI architectures for fast computation of the discrete Fourier transform and its inverse”, IEEE Tran. on Acoustics, Speech, and Signal Processing, vol.48, Issue 11, pp.3206-3216, Nov. 2000.
[16]J. W. Cooley and J. W. Tukey, “An algorithm for machine computation of complex Fourier series”, in Proc. Math. Computation, vol.19, April 1965, pp. 297–301.
[17]G.-D. Wu and Y. Lei, “Low power pipelined radix-2 FFT processor for speech recognition”, IEEE/SMC Int.Conf. on System of Systems Engineering, April 2006. pp. 299–303.
[18]Y.-H. Lee, T.-H. Yu, K.-K. Huang, and A.-Y. Wu, “Rapid IP design of variable-length cached-FFT processor for OFDM-based communication systems”, in Proc. IEEE Workshop on Signal Processing Systems Design and Implementation, Oct 2006, pp. 62 – 65.
[19]A. V. Oppenheim, R. W. Schafer, and J. R. Buck, “Discrete-Time Signal Processing (2nd Edition)”, Feb 1999.
[20]H.-F. Lo, M.-D. Shieh, and C.-M. Wu, “Design of an efficient FFT processor for DAB system”, in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), vol.4, May 2001, pp.654 – 657.
[21]P.-Y. Tsai, T.-H. Lee, and T.-D. Chiueh, “Power-Efficient Continuous-Flow Memory-Based FFT Processor for WiMax OFDM Mode”, in Proc. Int. Symposium on Intelligent Signal Processing and Communications (ISPACS), Dec. 2006, pp.622-625.
[22]C.-L. Wey, W.-C. Tang, and S.-Y. Lin, “Efficient VLSI Implementation of Memory-Based FFT Processors for DVB-T Applications”, in Proc. IEEE Computer Society Annual Symposium on VLSI, March 2007 pp.98-106.
[23]C.-L. Wey, W.-C. Tang, and S.-Y. Lin, “Efficient Memory-Based FFT Architectures for Digital Video Broadcasting (DVB-T/H)”, in Proc. Int. Symposium on VLSI Design, Automation and Test, April 2007, pp.1-4.
[24]S. Lee, H. Kim, and S.-C. Park, “Design of Power-efficient Memory-based FFT Processor with New Memory Addressing Scheme”, in Proc. Asia-Pacific Conference on Communications, Aug. 2006, pp.1-5.
[25]A. Delaruelle, J. Huisken, J. van Loon, F. Welten, “A channel demodulator IC for digital audio broadcasting”, in Proc. IEEE Custom Integrated Circuits Conference, May 1994, pp.47-50.
[26]Yu-Wei Lin, Hsuan-Yu Liu, Chen-Yi Lee, “A Dynamic Scaling FFT Processor for DVB-T Applications”, IEEE JSSC, vol 39, No. 11, pp. 2005-2013, Nov. 2004. 14.
[27]楊耀先, “可自我測試且具成本效益之記憶體式快速傅利葉轉換處理器設計”, 國立中央大學電機工程研究所碩士論文, July 2007.
[28]龍緒祥, “正交分頻多工通訊中之盲目頻域等化器”, 國立中央大學電機工程研究所碩士論文, July 2005.