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研究生:羅勝名
研究生(外文):Sheng-ming Luo
論文名稱:砷化鎵高速電子遷移率之電晶體微波/毫米波放大器設計
論文名稱(外文):Microwave/Millimeter-wave Amplifier using GaAs HEMT device
指導教授:詹益仁詹益仁引用關係張鴻埜
指導教授(外文):Yi-Jen ChanHong-Yeh Chang
學位類別:碩士
校院名稱:國立中央大學
系所名稱:電機工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:96
語文別:中文
論文頁數:92
中文關鍵詞:低雜訊放大器電感提升分佈式放大器
外文關鍵詞:distributed amplifierlow noise amplifieinductive peaking
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近年來無線通訊的迅速發展,微波與毫米波元件議題日漸重要。本論文主要討論0.15 um MHEMT製程與0.15 um PHEMT製程在射頻電路低雜訊放大器上應用,並利用0.5 um PHEMT製程設計加入電感提升的分佈式放大器,希望可以解決高頻率的小訊號增益,改善通訊系統中各級輸出的訊號的強度。
第一章為整篇論文的緒論,第二章分析0.15 um MHEMT製程的小訊號特性,使用HP IC-CAP軟體,搭配HP-8510C網路分析儀與HP-4142B直流分析儀量測元件的高頻特性,並將萃取出來的小訊號模型,於第三章分別設計成K頻段與Q頻段的低雜訊放大器,再與第四章利用0.15 um PHEMT製程所設計的K頻段低雜訊放大器做比較,同時也設計K頻段功率放大器,希望可以和低雜訊放大器一起整合在汽車雷達通訊系統中,第五章則是利用0.5 um PHEMT製程以電感提升的方式設計疊接分佈式寬頻放大器,希望電感提升的設計方式可以達到相當寬的頻寬,再使用90 nm CMOS 製程,希望實現有80 GHz的頻寬。
近年來無線通訊的迅速發展,微波與毫米波元件議題日漸重要。本論文主要討論0.15 um MHEMT製程與0.15 um PHEMT製程在射頻電路低雜訊放大器上應用,並利用0.5 um PHEMT製程設計加入電感提升的分佈式放大器,希望可以解決高頻率的小訊號增益,改善通訊系統中各級輸出的訊號的強度。
第一章為整篇論文的緒論,第二章分析0.15 um MHEMT製程的小訊號特性,使用HP IC-CAP軟體,搭配HP-8510C網路分析儀與HP-4142B直流分析儀量測元件的高頻特性,並將萃取出來的小訊號模型,於第三章分別設計成K頻段與Q頻段的低雜訊放大器,再與第四章利用0.15 um PHEMT製程所設計的K頻段低雜訊放大器做比較,同時也設計K頻段功率放大器,希望可以和低雜訊放大器一起整合在汽車雷達通訊系統中,第五章則是利用0.5 um PHEMT製程以電感提升的方式設計疊接分佈式寬頻放大器,希望電感提升的設計方式可以達到相當寬的頻寬,再使用90 nm CMOS 製程,希望實現有80 GHz的頻寬。
中文摘要 I
英文摘要 II
目錄 III
圖目錄 V
表目錄 VIII
第一章 緒論 1
1.1研究背景與動機 1
1.2 相關研究發展 3
1.3 論文架構 3
第二章 變異性(METAMORPHIC)高電子遷移率電晶體之小訊號模型建立 5
2.1 簡介 5
2.2 小訊號模型與建立流程 5
2.3 變異性高電子電晶體小訊號模型與雜訊模型建立 7
2.3.1外部寄生元件參數萃取流程與結果 7
2.3.2內部寄生元件參數萃取流程與結果 13
2.3.3雜訊指數模型與萃取結果 19
2.4 結果與討論 21
第三章 利用變異性(METAMOPHIC)高速電子遷移率電晶體設計K頻段、Q頻段低雜訊放大器設計 23
3.1 簡介 23
3.2 K頻段、Q頻段之低雜訊放大器設計概念 24
3.3 K頻段、Q頻段之低雜訊電路設計 24
3.3.1 元件選擇 24
3.3.2 設計方法 26
3.4 K頻段、Q頻段之低雜訊電路模擬與量測結果 27
3.5 結果與討論 33
第四章 利用假晶格(PSUEDOMOPHIC)高電子遷移率電晶體設計K頻段低雜訊放大器與功率放大器 35
4.1 簡介 35
4.2 K頻段之低雜訊放大器與功率放大器設計概念 35
4.3 K頻段之低雜訊放大器與功率放大器電路設計 35
4.3.1 K頻段之低雜訊放大器電路設計 35
4.3.2 K頻段之功率放大器電路設計 38
4.4 K頻段之低雜訊放大器與功率放大器電路模擬與量測結果 40
4.4.1 K頻段之低雜訊放大器模擬與量測結果 40
4.4.2 K頻段之功率放大器模擬與量測結果 43
4.5結果與討論 47
4.5.1 K頻段之低雜訊放大器之結果與討論 47
4.5.2 K頻段之功率放大器之結果與討論 48
第五章 疊接分佈式寬頻放大器設計 51
5.1簡介 51
5.2疊接分佈式寬頻放大器設計概念 52
5.3疊接分佈式寬頻放大器設計流程 55
5.4疊接分佈式寬頻放大器模擬結果與佈局 59
5.4.1 兩級疊接分佈式寬頻放大器模擬結果與佈局圖 59
5.4.2 六級疊接分佈式寬頻放大器模擬結果與佈局圖 61
5.4.3 CMOS疊接分佈式放大器模擬與佈局圖 63
5.5疊接分佈式寬頻放大器量測結果 65
5.5.1兩級疊接分佈式寬頻放大器量測結果 65
5.5.2六級疊接分佈式寬頻放大器量測結果 69
5.6結論 73
第六章 結論 75
參考文獻 77
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