臺灣博碩士論文加值系統

摘要

本論文中，提出一個算盤式數位類比轉換器，該數位類比轉換器的架構使用的是切換式電流源式數位類比轉換器，切換式電流源式的優點在於能維持在高速、低功率耗損的功效，論文中數位類比轉換器主要是應用中國式算盤的演算法，可以大幅簡化矩陣式數位類比轉換器所需要的編/解碼電路，進而減少電路的面積及提高電路的速度。
本論文的模擬環境是使用TSMC0.35,0.18μm製程，操作時脈每秒一百萬次取樣速率數位類比轉換器，分別完成4、6、8位元數位類比轉換器，本論文使用算盤式編碼器完成數位類比轉換器的設計，以4位元編碼器電路與傳統的溫度計式編碼器電路做比較，算盤式電晶體數目方面減少24顆、5%電晶體，與矩陣式比較減少4顆、0.3%電晶體，功率方面算盤式編碼器比較溫度計及矩陣式編碼器各減少1.15%及0.5%的功率，8位元算盤式與溫度計式比較減少70顆、8%的電晶體，與矩陣式減少8顆、0.2%電晶體，功率方面算盤式編碼器比較溫度計及矩陣式編碼器各減少25%及18%的功率，由上述模擬結果得知位元數愈多，減少的電晶體數目及功率愈多，本論文提出算盤式編解碼電路可以降低電路複雜度、功率耗損、減少電晶體數目，並且提高整體數位類比轉換器的速度，非常適合於高速低功率的應用。

Abstract

This paper proposes a Chinese abacus digital to analog converter. The prototype of the proposed circuit is used a switch-current digital to analog converter which the advantage is keeping high speed, low power consumption, respectively. The operation of the digital to analog converter uses the algorithm of the traditional Chinese abacus in the thesis. Comparing with a digital to analog converter (DAC) which is using the Matrix algorithm, the proposed algorithm of the novel Chinese abacus digital to analog converter can highly reduce the number of encode/decode logics which result in decreasing circuit area and increasing speed.
The simulation environment of the proposed circuit uses the TSMC 0.18μm and 0.35μm processes. The goal of the research is to design the 100MHz sampling rate per second of the digital to analog converter, he thesis dividedly uses the four, six, eight bits to complete the Chinese abacus digital to analog converter. The paper use Chinese abacus type encoder completes digital to analog converter design, does by four bit encoder circuit and the traditional thermometer type encoder circuit compares, the Chinese abacus type transistor number aspect reduces 24, 5%transistor numbers, reduces 4, 0.3% transistors with the matrix form comparison, the power aspect Chinese abacus type encoder comparison temperature takes into account the matrix form encoder to reduce 1.15% and 0.5% power respectively, eight bit Chinese abacus type and the thermometer type comparison reduces 70, 8% transistors, reduces 8. 0.2% transistors with the matrix, the power aspect abacus type encoder comparison temperature takes into account the matrix form encoder to reduce 18% and 25% powers respectively, are more by the above simulation result knowing bit number, the transistor number which and the power reduces much, the paper proposed that the Chinese abacus type arranges the encoding circuit to be possible to reduce the circuit order of complexity, the power to consume, the reduced transistor number, and increase the whole digital to analog converter speed, very suitably in high speed low power application.

CONTENTS

CHINESE ABSTRACT......i
ENGLISH ABSTRACT......ii
ACKNOWLEDGMENTS.......iv
CONTENTS..............v
LIST OF FIGURES.......ix
LIST OF TABLES........xiii

CHAPTER 1 INTRODUCTION..........1
1.1 Background..................1
1.2 Organization of the Thesis.....2
CHAPTER 2 REVIEW OF DIGITAL TO ANALOG CONVERTER......4
2.1 Ideal D/A Converter............4
2.2 Digital to Analog Converters of Characteristics and Parameters.............6
2.2.1 Resolution.......6
2.2.2 Accuracy.........6
2.2.3 Offset error.....6
2.2.4 Gain error.......7
2.2.5 Differential nonlinearity error DNL............8
2.2.6 Integral nonlinearity error INL................9
2.2.7 Settling time..................................9
2.2.8 Glitches.......................................10
2.2.9 Dynamic Range (DR).............................10
2.2.10 Signal-to-noise ratio (SNR)...................11
2.2.11 Effective number of bit (ENOB)................11
2.2.12 Spurious Free Dynamic Range (SFDR)............11
2.2.13 Conversion rate...............................13
2.2.14 Monotonicity..................................14
2.3 Digital to Analog Converters Architecture........14
2.3.1 Resistor-String DAC............................14
2.3.2 R-2R ladders DAC...............................15
2.3.3 Binary-weighted resistor DAC...................16
2.3.4 Current cell matrix DAC........................17
2.3.5 Charge-redistribution switched-capacitor DAC...18
2.3.6 Current mode binary-weighted code DAC..........18
2.3.7 Current mode thermometer code DAC..............20
2.3.8 Binary and thermometer segment DAC.............21
CHAPTER 3 THE DESIGN OF CHINESE ABACUS DIGITAL TO ANALOG CONVERTER............................................24
3.1 The Operation Principle of Chinese Abacus........24
3.2 Proposed Architecture of the Chinese Abacus digital to analog converter.....................................26
3.3 BA module........................................29
3.4 Switch will produce the glitch influence by digital to analog
converter............................................31
3.5 Four Bit Digital to Analog Converter Architecture.32
3.6 Six Bit Digital to Analog Converter Architecture..34
3.7 Eight Bit Digital to Analog Converter Architecture.37
CHAPTER 4 SIMULATION AND IMPLEMETATION.................40
4.1 Simulation Results.................................40
4.1.1 HSPICE Simulation................................40
4.1.2 Pre-Sim Simulation Results.......................42
4.1.3 Po-Sim Simulation Results........................45
4.1.4 Comparison.......................................46
4.1.5 Chip Layout Consider Results.....................47
4.2 Six bit Digital to Analog Converter Architecture (1) .................................................52
4.2.1 HSPICE Simulation................................52
4.2.2 Pre-Sim Simulation Results.......................53
4.2.3 Comparison.......................................54
4.2.4 Chip Layout......................................55
4.3 Six bit Digital to Analog Converter Architecture (2) ................................................58
4.3.1 Pre-Sim Simulation Results.......................58
4.3.2 Po-Sim Simulation Results........................61
4.3.3 SFDR Simulation Results..........................62
4.3.4 Comparison.......................................63
4.3.5 Chip Layout......................................65
4.4 TSMC 0.35m Eight bit Digital to Analog Converter Architecture...........................................67
4.4.1 HSPICE Simulation................................67
4.4.2 Pre-Sim Simulation Results.......................68
4.4.3 SFDR Simulation Results..........................69
4.4.4 Comparison.......................................71
4.4.5 Chip Layout......................................72
4.5 TSMC 0.18m Eight bit Digital to Analog Converter Architecture...........................................74
4.5.1 HSPICE Simulation................................74
4.5.2 Pre-Sim Simulation Results.......................75
4.5.3 Po-Sim Simulation Results........................78
4.5.4 SFDR Simulation Results..........................79
4.5.5 Comparison.......................................81
4.5.6 Chip Layout......................................83
4.6 The Chinese Abacus Encoder Architecture Comparison Results................................................85
4.7 Measurement Results of the Digital to Analog Converter……..........................................90
CHAPTER 5 CONCLUTIONS..................................92
REFERENCE..............................................93
LIST OF FIGURES

Figure 2.1 Idea DAC converter architecture......4
Figure 2.2 DAC offset error.....7
Figure 2.3 DAC gain error.......8
Figure 2.4 Differential nonlinearity error DNL..8
Figure 2.5 Integral nonlinearity error INL......9
Figure 2.6 Dynamic Range (DR).....10
Figure 2.7 Spurious Free Dynamic Range (SFDR)....12
Figure 2.8 Resistor-String DAC Architecture......15
Figure 2.9 R-2R ladders DAC Architecture.........16
Figure 2.10 Binary-weighted DAC Architecture.....16
Figure 2.11 Current cell matrix DAC Architecture..17
Figure 2.12 Charge-redistribution switched-capacitor DAC Architecture.....................................18
Figure 2.13 Current mode binary-weighted code DAC Architecture.....................................19
Figure 2.14 Matching and glitch problems of a binary-weighted DAC.....................................19
Figure 2.15 current mode thermometer code DAC Architecture.....................................21
Figure 2.16 Normalized required area versus percentage of segmentation.....................................22
Figure 3.1 A commonly used Chinese Abacus........25
Figure 3.2(a) Chinese abacus coding with base 10 of the decimal number 8, (b) the decimal number
7......................26
Figure 3.3 The proposed Chinese abacus adder coding rule with base 16...........28
Figure 3.4 The proposed abacus representation of decimal number 6...............28
Figure 3.5 The binary to abacus transformation of BA module...........................................30
Figure 3.6 The current source architecture.......31
Figure 3.7 The unit current source of the DAC....33
Figure. 3.8 .four bit digital to analog converter construction.....................................34
Figure 3.9 The unit current source of the DAC....35
Figure. 3.10 .Six bit digital to analog converter construction.....36
Figure. 3.11 Six bit digital to analog converter construction.....37
Figure 3.12 The unit current source of the DAC...38
Figure. 3.13 Eight bit digital to analog converter construction.....................................39
Figure 4.1 The HSPICE simulation of proposed 4-bit digital to analog converter which is tested by all input patterns.41
Figure 4.2 The HSPICE simulation of proposed 4-bit digital to analog converter function..............................41
Figure 4.3 The differential non-linear error..............42
Figure 4.4 The integral non-linear error..................42
Figure 4.5 The differential non-linear error..............43
Figure 4.6 The integral non-linear error..................43
Figure 4.7 The differential non-linear error..............44
Figure 4.8 The integral non-linear error..................44
*Figure 4.9 45
Figure 4.10 The integral non-linear error.................45
Figure 4.11 Two-dimensional spaces gradient error.........48
Figure 4.12 Two-dimensional parabolic gradient error......48
Figure 4.13 Converter Layout..............................50
Figure 4.14 Chip Layout Architecture......................50
Figure 4.15 Chip Layout...................................51
Figure 4.16 The HSPICE simulation of proposed 6-bit digital to analog converter which is tested by all input patterns.52
Figure 4.17 The HSPICE simulation of proposed 6-bit digital to analog converter function..............................53
Fig 4.18 The differential non-linear error................53
Figure 4.19 The integral non-linear error.................54
Figure 4.20 Converter Layout..............................55
Figure 4.21 Chip Layout...................................56
Figure 4.22 Chip Layout implemented.......................57
Fig 4.23 The differential non-linear error................58
Figure 4.24 The integral non-linear error.................58
Fig 4.25 The differential non-linear error................59
Figure 4.26 The integral non-linear error.................59
Fig 4.27 The differential non-linear error................60
Figure 4.28 The integral non-linear error.................60
Fig 4.29 The differential non-linear error................61
Figure 4.30 The integral non-linear error.................61
Figure 4.31 Sinewave spectrum for Fs=200MSample/s, fin=59MHz.................................................62
Figure 4.32 Sinewave spectrum for Fs=200MSample/s, fin=97MHz.................................................63
Figure 4.33 Converter Layout..............................65
Figure 4.34 Chip Layout...................................66
Figure 4.35 The HSPICE simulation of proposed 8-bit digital to analog converter which is tested by all input patterns.67
Figure 4.36 The HSPICE simulation of proposed 8-bit digital to analog converter function..............................68
Figure 4.37 The integral non-linear error.................68
Fig 4.38 The differential non-linear error................69
Figure 4.39 Sinewave spectrum for Fs=100MSample/s,fin=11MHz.................................70
Figure 4.40 Sinewave spectrum for Fs=100MSample/s, fin=30MHz.................................................70
Figure 4.41 Sinewave spectrum for Fs=100MSample/s, fin=51MHz.................................................71
*Table 4.7 Simulation results of 8-bit digital to analog converter.................................................71
Figure 4.42 Converter Layout..............................72
Figure 4.43 Chip Layout...................................73
Figure 4.44 The HSPICE simulation of proposed 8-bit digital to analog converter which is tested by all input patterns..................................................74
Figure 4.45 The HSPICE simulation of proposed 8-bit digital to analog converter function..............................75
Fig 4.46 The differential non-linear error................75
Figure 4.47 The integral non-linear error.................76
Fig 4.48 The differential non-linear error................76
Figure 4.49 The integral non-linear error.................77
Fig 4.50 The differential non-linear error................77
Figure 4.51 The integral non-linear error.................78
Fig 4.52 The differential non-linear error................78
Figure 4.53 The integral non-linear error.................79
Figure 4.54 Sinewave spectrum for Fs=100MSample/s, fin=11MHz.................................................80
Figure 4.55 Sinewave spectrum for Fs=100MSample/s, fin=31MHz.................................................80
Figure 4.56 Sinewave spectrum for Fs=100MSample/s, fin=51MHz.................................................81
Figure 4.57 Converter Layout..............................83
Figure 4.58 Chip Layout...................................84
Figure 4.59 measurement Settling time and DNL,INL driftage..................................................90
Figure 4.60 measurement SFDR driftage.....................91
Figure 4.9 The differential non-linear error ....45
Figure 4.10 The integral non-linear error...45
Figure 4.11 Two-dimensional spaces gradient error...48
Figure 4.12 Two-dimensional parabolic gradient error...48
LIST OF TABLES

Table 1.1 Signal-to-noise reduction ratio as a function of distortion products.......................................13
Table 1.2 Thermometer-code representations for 3-bit binary values....................................................20
Table 1.3 Area requirement for binary-weighed and thermometer-coded DAC.....................................22
Table 3.1 The truth table of BA module....................30
Table 4.1 Simulation results of 4-bit digital to analog converter.................................................46
Table 4.2 The circuit characteristic to show..............47
Table 4.3 The circuit characteristic to show..............54
Table 4.4 Simulation results of 6-bit digital to analog converter.................................................63
Table 4.5 The Comparison circuit characteristic to show...64
Table 4.6 The circuit characteristic to show..............64
Table 4.7 Simulation results of 8-bit digital to analog converter.................................................71
Table 4.8 The Comparison circuit characteristic to show...72
Table 4.9 Simulation results of 8-bit digital to analog converter.................................................81
Table 4.10 The Comparison circuit characteristic to show..82
Table 4.11 The circuit characteristic to show.............82
Table 4.12 The Chinese abacus and thermometer encoder comparison results........................................86
Table 4.13 The Chinese abacus and matrix encoder comparison results...................................................87
Table 4.14 The Chinese abacus and thermometer encoder comparison results........................................88
Table 4.15 The Chinese abacus and matrix encoder comparison results...................................................89

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