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研究生:高子為
研究生(外文):Tzi-Wei Kao
論文名稱:在系統階層中使用混合正負觸發緣時脈信號之峰值電流最佳化研究
論文名稱(外文):Peak Current Reduction by Using Hybrid-Edge Clock Technique in the System Design Flow
指導教授:吳宗益
指導教授(外文):Tzung-Yi Wu
學位類別:碩士
校院名稱:國立彰化師範大學
系所名稱:電子工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2007
畢業學年度:96
語文別:中文
論文頁數:46
中文關鍵詞:峰值電流電遷移電壓降上升緣觸發訊號下降緣觸發訊號
外文關鍵詞:peak currentelectro migrationIR dropground bouncerising triggered edgefalling triggered edge
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隨著製程進步以及晶片功能需求日益複雜,單位面積的電晶體(Transistor)比例急劇提昇使得電路中同步觸發(Simultaneous Switching)的電晶體數目也將隨之增加。在SoC系統中,設計者經常利用時脈的上升緣攫取資料,所以會有太多的暫存器同時更新資料並傳遞該資料給組合電路來做運算。因此造成過多的邏輯閘密集動作,以至於會有巨大的峰值電流產生且容易造成電遷移(Electro Migration)、晶片的自熱(Self-Heat)、電壓降(IR Drop)與接地彈跳(Ground Bounce)等問題。若能將電路內部的每個模組之用電時間錯開,便能將有效的降低峰值電流。
在本文中提出使用混合正負觸發緣之時脈的概念,將部份模組使用上升緣觸發訊號,部份模組使用下降緣觸發訊號以降低峰值電流。本論文提出Integer Linear Programming、Greedy Algorithm 1、New Greedy Algorithm 1、Greedy Algorithm 2和New Greedy Algorithm 2這些演算法來挑選電路中每個模組之時脈觸發緣。實驗結果顯示此方法可以有效改善的峰值電流。
As process technology progresses to ultra deep sub-micron, the number of transistors in unit's area is promoted sharply. The number of transistors that simultaneous switching also increases in the circuit. In a SoC system, the designer minutely uses rising edge to acquire data; therefore too many Flip-Flops simultaneously renew the data and transmit the data to combination circuit. For this reason there are many issues that need to challenge in the ultra deep sub-micron circuit, such as the enormous peak current. The enormous peak current will cause the problems, such as electro migration, self-heat in chip, IR drop and ground bounce. If the switch time of circuits in each module can be staggered, then it can effective reduce the peak current.
In this thesis, I propose a hybrid-edge clock technique that can decide some modules using rising triggered edge and some modules using falling triggered edge in order to reduce peak current. I proposed many algorithms(Integer Linear Programming, Greedy Algorithm 1, New Greedy Algorithm 1, Greedy Algorithm 2 and New Greedy Algorithm 2)to choose clock triggered edge in the circuit in each module. After the process of the algorithm, the peak current of the circuit can be effective reduced.
中文摘要 i
Abstract ii
致謝 iii
目錄 iv
圖目錄 vi
表目錄 viii

第一章 緒論 1
1-1 研究背景 1
1-2 研究動機 2
1-3 全文架構 3

第二章 相關文獻 5

第三章 問題概述與系統架構 10
3-1 問題概述 10
3-2 系統架構 13
3-3 輸出入資料檔 14

第四章 峰值電流最佳化之技術與演算法 19
4-1 Integer Linear Programming與Linear Programming 19
4-2 Greedy Algorithm 1和New Greedy Algorithm 1 24
4-3 Greedy Algorithm 2和New Greedy Algorithm 2 28

第五章 實驗結果與分析 33
5-1 工作平台與系統環境 33
5-2 實驗結果與數據分析 33

第六章 結論 43

參考文獻 44

作者簡歷 46
[1] P. Heydari and M. Pedram, “Ground Bounce in Digital VLSI Circuits,” IEEE Trans. On VLSI System, vol. 11, no. 2, pp. 180-193, April 2003.

[2] S. Chowdhury and J.S. Barkatullah, “Estimation of Maximum Currents in MOS IC Logic Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 9, no. 2, pp. 642-654, June 1990.

[3] Harish Kirplani, Farid N. Najm, and Ibrahim N. Hajj, “Pattern Independent Maximum Current Estimation in Power and Ground Buses of CMOS VLSI Circuits: Algorithms, Signal Correlations, and Their Resolution,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 14, no. 8, pp. 998-1012, August 1995.

[4] P. Vuillod, L Benini, A Bogliolo and G. Micheli, “Clock-skew optimization for peak current reduction,” Low Power Electronics and Design, pp.265-270, August 1996.

[5] W.-C.D. Lam, Koh C.-K., and C.-W.A. Tsao, “Power Supply Noise Suppression via Clock Skew Scheduling,” International Symposium on Quality Electronic Design, pp. 355-360, March 2002.

[6] W.-C.D. Lam, Koh C.-K., and C.-W.A. Tsao, “Clock Scheduling for Power Supply Noise Suppression using Genetic Algorithm with Selective Gene Therapy,” International Symposium on Quality Electronic Design, pp. 327-332, March 2003.

[7] Y.T. Nieh, S.H. Huang and S.Y. Hsu, “Minimizing Peak Current via Opposite-Phase Clock Tree,” Design Automation Conference (DAC), pp. 182-185, June 2005.

[8] Jiun-Kuan Wu and Tsung-Yi Wu, “Peak Current Reduction Technique by Flip-Flop Replacement,” 13th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), pp. 141-145, Japan, April 2006.

[9] A. Vittal, H. Ha, F. Brewer and M. Marek-Sadowska, “Clock Skew Optimization for Ground Bounce Control,” Computer-Aided Design, 1996. ICCAD-96. Digest of Technical Papers, IEEE/ACM International Conference, pp. 395-399, Nov. 1996.

[10] Jiun-Kuan Wu, Liang-Ying Lu, Kuang-Yao Chen and Tsung-Yi Wu, “A Flip-Flop Replacement Technique for IR Drop Reduction,” The 18th VLSI Design/CAD Symposium, Taiwan, pp. 200-203, August 2007.
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