臺灣博碩士論文加值系統

近十年來，隨著製程技術的演進，電晶體的體積越變越小，由於物理特性，導致這些體積縮小的電晶體之漏電功耗（Leakage Power）已經趕上了動態功耗（Dynamic Power）。對於可攜性的電子系統而言，漏電功耗的大小會影響電子系統內部電池使用的時間長短，所以如何減少晶片的漏電功耗便成為一項重要的課題。
在互補式金屬氧化半導體中，影響漏電功耗大小的原因主要有閘極氧化層厚度、臨界電壓（Threshold Voltage）、製程技術等。多種的臨界電壓元件庫（Multiple Threshold Voltage Libraries）之技術是一項利用多種的臨界電壓元件庫對電路做閘替換來改善漏電功耗之技術，本論文所提的方法會先利用多種的臨界電壓元件庫之技術對電路做閘替換，以便減少電路的漏電功耗，接著會使用我們所設計出來的兩種不同型式的混和臨界電壓之標準元件庫（Hybrid Threshold Voltage Standard Cell Libraries，HTVSCLs）和與之搭配的演算法再次對電路做漏電功耗的最佳化處理，如此一來，便可以得到比單純使用多種的臨界電壓元件庫之技術還要好的結果。

Due to the evolution of the process technology in the recent ten years, the transistor size shrinks. Because of the physical characteristics, the leakage power of small transistors is comparable to its dynamic power. In a portable electronic system, the magnitude of the leakage power will influence the working time of the battery inside the electronic system. So how to reduce the leakage power of a chip has become an important issue.
In the complementary metal-oxide-silicon (CMOS), the major reason to affect the magnitude of the leakage power is gate-oxide thickness, threshold voltage, and process technology. The technology of the multiple threshold voltage libraries is to utilize multiple threshold voltage libraries to do gate replacement in a circuit to cut down the leakage power consumption. In order to reduce leakage power of the circuit, this thesis proposes a new method. Firstly, it uses the technology of multiple threshold voltage libraries to do gate replacement. Then two kinds of hybrid threshold voltage standard cell libraries and an algorithm are used to optimize the leakage power of a circuit. It can obtain a better result than that only using the technology of multiple threshold voltage libraries.

中文摘要 i
英文摘要(Abstract) ii
致謝 iii
目錄 iv
圖目錄 vi
表目錄 viii

第一章 緒論 1
1-1 研究背景 1
1-2 研究動機與目的 2
1-3 論文架構 6

第二章 功耗與漏電流的相關理論 8
2-1 功耗的組成 8
2-2 功耗的定義 9
2-3 功耗的介紹 9
2-4 功耗的計算 11
2-5 電晶體內部漏電流的分析 11

第三章 時序的相關理論 14
3-1 時間的定義 14
3-2 延遲模型 17
3-3 時序路徑的判斷 18
3-4 時序限制 19
3-5 時序的分析 20

第四章 相關文獻的探討 23

第五章 五種形式的標準元件庫 25

第六章 漏電流最佳化之技術與演算法 28
6-1 多種臨界電壓元件庫之技術 28
6-1-1 多種臨界電壓元件庫的演算法 28
6-1-2 邏輯閘成本的計算 31
6-2混和臨界電壓元件庫之技術 31
6-2-1 第一種混和臨界電壓元件庫的方法 31
6-2-2 第一種混和臨界電壓元件庫的演算法 32
6-2-3 第二種混和臨界電壓元件庫的方法 33
6-2-4 第二種混和臨界電壓元件庫的演算法 34

第七章 系統的架構 35

第八章 實驗結果與分析 36
8-1 工作平台與系統環境 36
8-2 實驗結果與數據分析 36

第九章 結論 47

參考文獻 48

作者簡歷 50
圖目錄
圖1.1：摩爾定律的趨勢圖 1
圖1.2：漏電功耗和動態功耗的比例圖 3
圖1.3：Power Gating的電路 5
圖1.4：MTCMOS電路 5
圖1.5：VTCMOS反相器 6
圖2.1：功耗的組成圖 8
圖2.2：短路電流發生的時段圖 10
圖2.3：切換功耗 10
圖2.4：電晶體內部漏電流組成示意圖 12
圖3.1：上升轉換時間和下降轉換時間 14
圖3.2：傳輸延遲時間和負的傳輸延遲時間 15
圖3.3：恢復時間 16
圖3.4：設定時間和保持時間 16
圖3.5：延遲時間的組成圖 17
圖3.6：簡單的時序路徑電路圖 18
圖3.7：簡單的時序序向電路圖 20
圖3.8：簡單的組合電路圖 21
圖5.1：三種臨界電壓的NAND2 26
圖5.2：第一種混和臨界電壓的NAND2 26
圖5.3：第二種混和臨界電壓的NAND2 27
圖6.1：多種臨界電壓演算法之虛擬碼 30
圖6.2：使用HYVT1邏輯閘的電路 32
圖6.3：HYVT1演算法之虛擬碼 33
圖6.4：使用HYVT2邏輯閘的電路 34
圖6.5：HYVT2演算法之虛擬碼 34
圖7.1：系統的架構圖 35
圖8.1：c7552 Benchmark Leakage Power 45
圖8.2：c7552 Benchmark Frequency 45
圖8.3：s38584 Benchmark Leakage Power 45
圖8.4：s38584 Benchmark Frequency 46
圖8.5：GUC2 Benchmark Leakage Power 46
圖8.6：GUC2 Benchmark Frequency 46
表目錄
表1.1：主要深次微米元件和相關問題的簡要列表 2
表1.2：各種臨界電壓的優、缺點 4
表8.1：實驗結果 40
表8.2：實驗結果 41
表8.3：實驗結果 42
表8.4：實驗結果 43
表8.5：實驗結果 44

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