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研究生:劉羽
研究生(外文):Yu Liu
論文名稱:應用於移動估測計算陣列的高可靠度內建自我測試/回復架構設計
論文名稱(外文):High-Reliability Built-in Self-Detecting/Correcting Architecture for Motion Estimation Computing Array
指導教授:許鈞瓏
指導教授(外文):Chun-Lung Hsu
學位類別:碩士
校院名稱:國立東華大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:96
語文別:中文
論文頁數:67
中文關鍵詞:自我測試運算編碼移動估測
外文關鍵詞:arithmetic codemotion estimationSelf-test
相關次數:
  • 被引用被引用:0
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近年來,隨著儲存媒體的容量提升以及科技的進步,多媒體的應用走向高畫質、高解析度的時代,且在高品質影像壓縮中,從MPEG-1到2003年所發佈的MPEG-4皆是強調影像高品質以及低位元率最好的應用。不單單如此,接著又出現壓縮品質更高的H.264影像編碼[1]-[3],它提供了一個比之前的任何視訊編碼標準更傑出的壓縮比例。而在上述的影像壓縮編碼中移動估測(Motion Estimation ; ME)是一個非常重要的核心功能方塊,此方塊又稱為移動估測計算陣列(Motion Estimation Computing Array ; MECA),其功用是用來去除畫面與畫面間的冗餘性來達成高壓縮率。然而他的高度計算需求是非常耗時的,為了加快計算的速度,龐大的處理單元陣列(Process Element Array; PE Array)是無可避免的,特別是在高解析度的裝置中,如Video CD、DVD、HDTV…等。因此當我們面對這麼重要且龐大的處理單元時,可測試性設計的問題將會變得越來越重要。
  本論文提出一種在移動估測陣列中自我偵測/回復的架構的設計,基於雙冗餘數運算編碼和低成本餘數商數運算編碼以達成錯誤偵測/回復,在移動估測計算陣列中的處理元件針對單一位元的錯誤與多位元錯誤,在線上時執行自我偵測和自我回復的電路,在效能的評估上,有較低的額外使用面積和時間的延遲以及
較少的生產量的遺失。
In the past year, following the capacity of multi-media storage and technology were improved, the applications of multi-media moved towards to a time of high quality and high resolution. Also in high quality of video compression, the MPEG-1 to MPEG-4 in 2003, all emphasized the high quality of video and low bit-rate. Not only the higher compression quality was appeared that was H.264 video coding but also the H.264 provided more outstanding compression quality than other standards of video coding. In the above mentioned, the motion estimation (ME) was a very important core block in video coding. Also, the core block was called motion estimation computing array (MECA) that was used to remove the redundant of frame to frame to achieve the high compression rate. But the computing of MECA had a great quantity and needed a lot of time. In order to increase the speed of computing, a lot of element array (PE array) was unable to avoid, especially in high video resolution such as Video CD, DVD, HDTV…etc. Hence, we face this so important and enormous process unit, the problem of testable design became more and more important.
This thesis develops a built-in self-detecting / correcting (BISDC) architecture design for motion estimation computing array (MECA). Based on the error-detecting / correcting concepts of bi-residue arithmetic codes and low cost remainder and quotient (RQ) arithmetic codes, any error of each processing element (PE) in MECA can be effectively detected and corrected on-line by using the proposed built-in self-detecting (BISD) and built-in self-correcting (BISC) circuits, respectively. Performance analysis and evaluation show the proposed BISDC architecture has little area overhead, timing penalty and very low throughput loss.
誌謝 I
摘要 III
ABSTRACT IV
論文目錄 V
圖目錄 VII
表目錄 IX
第一章 導論 1
1.1 研究動機 1
1.2 研究目標 4
1.3 國內外研究現狀 5
1.4 論文架構 7
第二章 相關研究與背景知識 9
2.1 內建自我測試簡介 9
2.2 影像系統移動估測計算陣列研究與架構 15
2.2.1 區塊比對(Block matching)概論 15
2.2.2 2D-FSBMA硬體架構 17
2.3 錯誤容忍 21
第三章 內建自我測試/回復架構設計 27
3.1 單一位元錯誤內建自我測試/回復 27
3.1.1 運算編碼 27
3.1.2 計算陣列單一位元內建自我測試/回復電路設計 33
3.2 多位元錯誤內建自我測試/回復 43
3.2.1 餘數、商基本定理 43
3.2.2 計算陣列多位元內建自我測試、回復電路設計 46
第四章 模擬結果與分析 59
4.1 額外使用面積(AREA OVERHEAD) 59
4.2 時序冗餘(TIMING REDUNDANCY) 61
4.3 生產量(THROUGHPUT) 62
4.4 可靠度分析 65
第五章 結論與未來展望 67
參考文獻 I
著作列表 V
[1]Joint Video Team, Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Specification, ITU-T Recommendation H.264 and ISO/IEC 14496-10 AVC, May 2003.
[2]Video Coding for Low Bit Rate Communication, Feb. 1998.
[3]Information Technology-Coding of Audio-Visual Objects-Part 2: Visual ISO/IEC 14 496-2, 1999.
[4]H. Hashempour and F.Lombardi, “Compression of VLSI Test Data by Arithmetic Coding, “ Proc. 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Oct, 2004, pp.150-157.
[5]I. E. G. Richardson, “H.264 and MPEG-4 video compression: Video Coding for Next Generation Multimedia.” Chichester, UK: John Wiley & Sons, 2003.
[6]Vishwani D. Agrawal, Charles R. Kime and Kewal K. Saluja, “A Tutorial on Built-in Self-Test. I. Principles” IEEE Transactions On Design and Test of Computers, pp.73-82, Jan. 1993.
[7]D. Li, M. Hu and, A. O. Mohemed, “Built-In Self-Test Design of Motion Estimation Computing Array,” Proc. The 2nd Annual IEEE Northeast Workshop on Circuit and System., June, 2004, pp. 349-352,.
[8]E. I. MeCluskey, “Built-In Self-Test Technique,” IEEE Design & Test of Computer, pp. 9-77, June 1993.
[9]C.-Y. Chen, S.-Y. Chien, Y.-W. Huang, T.-C. Chen, T.-C. Wang, and L.-G. Chen, “Analysis and architecture design of variable block-size motion estimation for H.264/AVC,“ IEEE Transactions on Circuits and Systems, Vol. 53, Issue 3, pp. 578-593, Mar., 2006.
[10]Y.-W. Huang, S.-Y. Chien, B.-Y. Hsieh, Lai, and L.-G. Chen, “Global elimination algorithm and architecture design for fast block matching motion estimation,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 14, Issue 6, pp. 898-907, June, 2004.
[11]N. Roma and L. Sousa, “Efficient and configurable full-search block-matching processors,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 12, Issue 12, pp. 1160-1167, Dec., 2002.
[12]J. H. Lee, K. W. Lim, B. C. Song, and J. B. Ra, “A fast multi-resolution block matching algorithm and its LSIarchitecture for low bit-rate video coding,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 11, Issue 12, pp. 1289-1301, Dec., 2001.
[13]J.-C. Tuan, T.-S. Cheng, and C.-W. Jen “On the data reuse and memory bandwidth analysis for full-searchblock-matching VLSI architecture,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 12, Issue 1, pp. 61-72, Jan, 2002.
[14]H. Yeo and Y. H. Hu, “A novel modular systolic array architecture for full-search block matching motion estimation,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 5, no. 5, pp. 407–416, Oct. 1995.
[15]Y.-K. Lai and L.-G. Chen, “A data-interlacing architecture with two-dimensional data-reuse for full-search block-matching algorithm,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 8, no. 2, pp. 124–127, Apr. 1998.
[16]L. D. Vos and M. Stegherr, “Parameterizable VLSI architectures for the fullsearch block-matching algorithm,” IEEE Transactions on Circuits and Systems, vol. 36, no. 2, pp. 1309–1316, Oct. 1989.
[17]T. Komarek and P. Pirsch, “Array architectures for block matching algorithms,” IEEE Transactions on Circuits and Systems, vol. 36, no. 10, pp. 1301–1308, Oct., 1989.
[18]C.-H. Hsieh and T.-P. Lin, “VLSI architecture for block-matching motion estimation algorithm,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 2, no. 2, pp. 169–175, June 1992.
[19]K.-M. Yang, M.-T. Sun, and L. Wu, “A family of VLSI designs for the motion compensation block-matching algorithm,” IEEE Transactions on Circuits and Systems, vol. 36, no. 2, pp. 1317–1325, Oct. 1989.
[20]Y.-S. Jehng, L.-G. Chen, and T.-D. Chiueh, “An efficient and simple VLSI tree architecture for motion estimation algorithms,” IEEE Transactions on Signal Processing, vol. 41, no. 2, pp. 889–900, Feb. 1993.
[21]Z. L. He, C. Y. Tsui, K. K. Chan, and M. L. Liou, “Low-power VLSI design for motion estimation using adaptive pixel truncation,” IEEE Transactions on Circuits Systems Video Technology, vol.10, no. 5, pp. 669-678, 2000.
[22]O. Stern and H. J. Wunderlich, “Simulation results of an efficient defect analysis procedure,” Proc. International Test Conference, Oct. 1994, pp. 729-738.
[23]Tung-Hsing Wu, Yi-Lin Tsai, and Soon-Jyh Chang “An Efficient Design-for-Testability Scheme for Motion Estimation in H.264/AVC,” VLSI Design, Automation and Test, 2007. VLSI-DAT 2007. International Symposium on , April, 2007, pp. 1-4.
[24]S. Chang, J.-H. Hwang, and C.-W. Jen, “Scalable array architecture design for full search block matching,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 5, no. 4, pp. 332–343, Aug. 1995.
[25]S. Y .Yap and J. V. McCanny, “A VLSI Architecture for Variable Block Size Video Motion Estimation,” IEEE Transactions on Circuits and Systems, vol.5 1, no.7, pp. 384-389, July 2004.
[26]M.A. Bayoumi, G.A. Jullien, and W.C. Miller, “A VLSI implementation of residue adders,” IEEE Transactions on Circuits and System, vol. 34, no. 3, pp. 284-8, Mar. 1987.
[27]Rajendra S. Katti, “A New Residue Arithmetic Error Correction Scheme,” IEEE Transactions on Computers, vol.45, no. 1, pp. 13-19, Jan. 1996.
[28]R.W. Watson and C.W. Hastings, “Residue Arithmetic and Reliable Computer Design.” Washington, D. C.: Spartan Books, 1967, to be published.
[29]P. Gallagher, V. Chickermane, S. Gregor, and T. S. Pierre, “A building block BIST methodology for SOC designs: a case study,” Proc. International Test Conference, Oct, 2001, pp. 111-120.
[30]R. J. Higgs, and J. F. Humphreys, “Two-error-location for quadratic residue codes,” IEE Proceedings Communications., vol.149, no. 3, pp. 129-131, June, 2002.
[31]J. C. Tuan, T. S. Chang, and C. W. Jen, “On the data reuse and memory bandwidth analysis for full-search block-matching VLSI architecture,” IEEE Transactions on Circuits and System Video Technology, vol. 12, no. 1, pp. 61-72, Jan. 2002.
[32]X. Li, J. Qin, B. Huang, X. Zhang, and J. B. Bernstein, “A new SPICE reliability simulation method for deep submicrometer CMOS VLSI circuits,” IEEE Transactions on Device and Materials Reliability, vol. 6, no. 2, pp. 247-257, June, 2006.
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