跳到主要內容

臺灣博碩士論文加值系統

(18.97.14.85) 您好!臺灣時間:2024/12/07 17:26
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

我願授權國圖
: 
twitterline
研究生:林秀菁
研究生(外文):Siou-Jing Lin
論文名稱:以需求分頁為機制之Minix3微核心
論文名稱(外文):Making Minix 3 a Demand-Paged Microkernel
指導教授:江明朝
指導教授(外文):Ming-Chao Chiang
學位類別:碩士
校院名稱:國立中山大學
系所名稱:資訊工程學系研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:96
語文別:英文
論文頁數:107
中文關鍵詞:微核心虛擬記憶體需求分頁
外文關鍵詞:MicrokernelDemand-PagingVirtual Memory
相關次數:
  • 被引用被引用:0
  • 點閱點閱:292
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
過去十年中,作業系統的研究已不再侷限於monolithic kernel這種架構,而越來越多朝向microkernel的研究,那是由於: (1) Microkernel 這種微核心架構讓作業系統變得容易了解與學習,(2) 因核心內包含的東西少,讓作業系統較容易移植,且更有彈性,容易依照需求加減功能,(3) 扮演重要角色的訊息傳遞程式已不再過分的拖慢系統速度。
Minix 3 就是在過去十年中發展出來的一套微核心系統,一開始是教育性質,以教學為主,但目前也朝向嵌入式系統發展。在架構上它仍以僅支援IA-32為主,但目前已有相關研究是將它移植到其他架構上[4, 8]。這篇論文主要在探討其記憶體管理,將原來只有segmentation方式的管理變成能夠支援虛擬記憶體—也就是paging。
因此此論文分成兩個部分:第一部分將先實作出一個獨立管理記憶體的程式—pg,在Minix 3 這種接下kernel工作的程式稱做server ; 管理記憶體對於monolithic kernel來說是必須在kernel內完成的。第二部分將依IA-32的硬體支援去實作segmentation with paging的記憶體管理模型。
Over the past decade, researches on operating systems have been shifted from monolithic kernels towards microkernels for several reasons. Of them are: (1) It is easier to understand and debug because the kernel is much smaller. (2) It is much more secure and flexible because the kernel is small, and most of the kernel functions can be implemented as servers running in the user space instead of in the kernel space. (3) The message passing technique that is in the core of the microkernel has been improved, and thus the overhead required for the message passing has been highly reduced.
Minix 3 is one of the microkernels developed over the past decade and is aimed for educational purpose and small PCs. It is implemented on the IA-32 architecture and is based on the segmented memory model of IA-32. The purpose of this thesis is to use Minix 3 as a case study and to convert the segmented memory model adopted by the current implementation to coexisted with the demand paged memory model, which is also supported by the IA-32 architecture. That said, the thesis can be divided into two parts: The first part is to implement a new server called pager, which would take over the memory management subsystem of the Minix 3 microkernel and be used to offload the overhead of the kernel. The second part is to implement a virtual memory management subsystem that uses the segmentation with paging memory model of the IA-32 architecture.
Chapter 1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Development Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2.1 Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2.2 Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2.3 Debugging Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Introduction to Minix 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3.1 The Original Design of Minix . . . . . . . . . . . . . . . . . . . . . 4
1.3.2 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3.3 System Call vs. Kernel Call . . . . . . . . . . . . . . . . . . . . . . 7
1.3.4 Memory Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.4 Introduction to IA-32 Architecture . . . . . . . . . . . . . . . . . . . . . . . 10
1.4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.4.2 Protected-Mode Memory Management . . . . . . . . . . . . . . . . 12
1.4.3 Segmentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.4.4 Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.4.5 Interrupt and Exception Handling . . . . . . . . . . . . . . . . . . . 19
Chapter 2 Implementation: Part One 21
2.1 A Standalone Memory Management Server: Pager . . . . . . . . . . . . . . 21
2.1.1 Modifying the Kernel and Booting Structures . . . . . . . . . . . . . 22
2.1.2 Building the Memory Management Server . . . . . . . . . . . . . . . 23
2.1.3 Ignoring the SIGTERM Signal . . . . . . . . . . . . . . . . . . . . . . 24
Chapter 3 Comparing the Implementations 26
3.1 Two Different Approaches for Page Allocation . . . . . . . . . . . . . . . . 26
3.2 Where Should the Page-Directory and Page-Table be? . . . . . . . . . . . . . 28
3.2.1 When User Process Making a System Call? . . . . . . . . . . . . . . 28
3.2.2 EIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.2.3 Paying Special Attention to Memory Copy Functions . . . . . . . . . 32
3.2.4 Who Is in Charge of the Memory? . . . . . . . . . . . . . . . . . . . 32
3.3 Virtual Memory Layout for Minix 3 . . . . . . . . . . . . . . . . . . . . . . 33
Chapter 4 Implementation: Part Two 35
4.1 Rethinking the Role of Memory Management Server . . . . . . . . . . . . . 35
4.2 Initializing the Page Directory and Page Table in Minix . . . . . . . . . . . . 42
4.3 A Primitive Virtual Memory System . . . . . . . . . . . . . . . . . . . . . . 44
4.3.1 How It Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.3.2 Filling up Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.3.3 Linear Address Copy . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.4 Page Fault and Dynamic Memory Allocation . . . . . . . . . . . . . . . . . 45
Chapter 5 Performance Evaluation 47
5.1 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Chapter 6 Related work 50
Chapter 7 Conclusion and Future Works 52
7.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
7.2 Future Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Appendix A Serial Port Driver 57
Appendix B Source Code of Benchmarks 59
B.1 Fork . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
B.2 Exec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
B.3 Matrix Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Appendix C Source Code of Pager 62
C.1 alloc.c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
C.2 const.h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
C.3 do alloc.c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
C.4 do exec.c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
C.5 do fork.c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
C.6 do free.c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
C.7 do segcopy.c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
C.8 free.c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
C.9 glo.h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
C.10 linear copy.s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
C.11 linear memzero.s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
C.12 main.c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
C.13 memcopy.s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
C.14 memzero.s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
C.15 misc.c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
C.16 pager.c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
C.17 pg.h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
C.18 proto.h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
C.19 segcopy.c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
C.20 table.c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
C.21 type.h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
[1] IA-32 Intel Architecture Software Developer’s Manual, volume 2. Intel Corporation,
June 2003.
[2] IA-32 Intel Architecture Software Developer’s Manual, volume 3. Intel Corporation,
June 2005.
[3] IA-32 Intel Architecture Software Developer’s Manual, volume 1. Intel Corporation,
June 2005.
[4] Ingmar A. Alting. A Port of the MINIX OS to the PowerPC Platform. September 2006.
[5] Dawson R. Engler, M. Frans Kaashoek, and James W. O’Toole Jr. The Operating System
Kernel as a Secure Programmable Machine. In Proceedings of the 6th workshop on ACM
SIGOPS European workshop: Matching operating systems to application needs, pages
62–67, Sep 1994.
[6] Dawson R. Engler, M. Frans Kaashoek, and James W. O’Toole Jr. Exokernel: An Op-
erating System Architecture for Application-Level Resource Management. pages 251–
166, 1995.
[7] Jorrit Herder. Towards a True Microkernel Operating System. Feb 2005.
[8] Ivan Kelly. Porting MINIX to Xen. May 2006.
[9] Jochen Liedtke. Improving IPC by Kernel Design. In Proceedings of the 14th Sympo-
sium on Operating Systems Principles, pages 175–188, 1993.
[10] Andrew S. Tanenbaum, Jorrit N. Herder, and Herbert Bos. Can We Make Operating
Systems Reliable and Secure? IEEE Computer, pages 44–51, May 2006.
[11] Andrew S. Tanenbaum and Albert S. Woodhull. Operating Systems Design and Imple-
mentation 3/E. pearson, 2006.
[12] Stephan Zeisset, Stefan Tritscher, and Martin Mariandres. A New Approach to Dis-
tributed Memory Management in the Mach Microkernel. In Proceedings of the Annual
Technical Conference on USENIX 1996 Annual Technical Conference, 1996.
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top