臺灣博碩士論文加值系統

由於能量消耗影響行動裝置的待機時間及電池的重量與成本，設計低功率的SOC成為一項重要的課題。目前的系統層級設計中尚未有成熟、商業化的功率消耗估計軟體供SOC開發人員使用。本論文提出一個系統層級的功率估計架構，能夠藉由使用者自訂的功率模型，自動化地提供功率估計的功能。本架構將SystemC模擬環境與功率估計分離成兩個同時運行的程序，首先依據使用者設定的功率參數自動產生一個收集資訊的SystemC模組，在模擬時自動從SystemC模擬環境中收集功率參數的數值傳送到功率估計程式，接著功率估計程式會根據使用者設定的功率計算公式算出功率消耗。使用者能夠藉由本功率估計架構快速地在原有之SystemC模擬環境中加入功率估計之功能，藉此分析其SOC系統中的功率消耗情況，找出改良重點，並且能夠在加入低功率設計後，利用本架構方便地比較與分析各種低功率設計的優缺點。本論文將此功率估計架構套用在一個3D繪圖SOC上，藉由分析此SOC之功率消耗驗證本功率估計架構的功能性與實用性。

Energy consumption will reduce the battery life time and increase the weight and cost of mobile devices. Low-power design methods become an important issue of SOC. Until now, there is no commercial power estimates software in system-level. Users must add power estimation to SystemC simulation environment by themselves. In this paper, we proposed a system-level power estimation framework. Users can use their custom power model, and add power estimation automatically. The proposed framework separates the SystemC simulation environment and power estimation into two independent procedures. First, we generate a data collection SystemC module automatically based on the parameters set up by users. This data collection module will automatically collect the information of parameters from SystemC simulation environment, and send these information to power estimation program. Power estimation program will calculate power consumption according to these parameters and formulas set by user. Users can add power estimation to their SystemC simulation environment quickly and use our framework to analysis the power consumption of their SOC system to find improvement issues. Users can use of our framework to compare and analyze various low-power design methods. In this paper, we applied our framework to estimate the power consumption of a 3D graphics SOC to authenticate the functional and practical ability of our framework.

Chapter 1 概論 ................................... 1
1.1 研究動機 ................................... 1
1.2 貢獻 ....................................... 2
1.3 論文大綱 ................................... 2
Chapter 2 研究背景與相關研究 ..................... 3
2.1 電子系統層級設計 ........................... 3
2.2 功率估計模型 ............................... 5
2.2.1 處理器 ................................. 6
2.2.2 匯流排 ................................. 9
2.2.3 記憶體 ................................ 10
2.2.4 系統層級功率估計方法 .................. 11
2.3 低功率設計方法 ............................ 14
2.3.1 Clock gating .......................... 14
2.3.2 電源管理 .............................. 15
Chapter 3 系統層級功率估計架構 .................. 17
3.1 功率估計架構 .............................. 17
3.2 功率資訊收集 .............................. 20
3.2.1 功率參數設定 .......................... 20
3.2.2 資訊收集模組與硬體元件的搭配 .......... 22
3.2.3 資訊累計與動態功率模型 ................ 23
3.3 功率消耗計算方法 .......................... 27
3.3.1 功率消耗計算公式 ...................... 27
3.3.2 功率資訊的取樣與計算 .................. 29
Chapter 4 功率估計架構之應用實例 ................ 33
4.1 3D繪圖SOC的SystemC模擬環境 ................ 33
4.2 3D繪圖SOC的功率估計模型 ................... 38
4.2.1 處理器的功率估計模型 .................. 38
4.2.2 匯流排的功率估計模型 .................. 38
4.2.3 記憶體的功率估計模型 .................. 41
4.2.3 ASIC的功率估計模型 .................... 44
4.3 3D繪圖SOC功率估計實例 ..................... 48
4.4 3D繪圖SOC搭配clock gating功率估計實例 ..... 50
4.5 3D繪圖SOC搭配電源管理功率估計實例 ......... 54
Chapter 5 結論與未來目標 ........................ 63
5.1 結論 ...................................... 63
5.2 未來目標 .................................. 63
參考文獻 .......................................... 65
附錄A 功率估計程式輸入格式與說明 ................. 68

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