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研究生:吳岳霖
研究生(外文):Yueh-Lin Wu
論文名稱:五千兆赫頻率合成器應用於WiMAX免執照頻段
論文名稱(外文):A 5GHz Frequency Synthesizer for Unlicensed Band of WiMAX
指導教授:郭可驥
指導教授(外文):Ko-Chi Kuo
學位類別:碩士
校院名稱:國立中山大學
系所名稱:資訊工程學系研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:96
語文別:英文
論文頁數:80
中文關鍵詞:除頻器壓控振盪器鎖相迴路電荷幫浦相位頻率偵測器
外文關鍵詞:PLLCharge PumpPulse Frequency DetectorVCOdivider
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本篇論文設計了一個低功率消耗與低相位雜訊全積體化除整數之頻率合成器,並利用充放電電流幫浦架構的鎖相迴路來組成。本頻率合成器主要應用於IEEE 802.16b WiMAX 5.725GHz至 5.825GHz免執照頻段,提供5.13GHz至5.22GHz的本地振盪器,並應用於射頻收發機的前端電路。本論文的頻率合成器包含相頻偵測器(PFD)、電荷幫浦(CP)、低通迴路濾波器(LPF)、壓控振盪器(VCO)以及含雙模數前置除頻器(dual-modulus prescaler)之pulse-swallow divider。電路設計中以新的架構來達到低功率消耗與低相位雜訊的壓控振盪器效能;而在除頻器方面並採用最佳化E-TSPC架構,使得除頻器可操作在維持高頻區且大幅降低功率的耗損。此頻率合成器採用TSMC 0.18μm 1P6M CMOS製程,整個晶片面積為1.1 mm2。
This thesis presents a low power consumption and low phase noise CMOS integer-N frequency synthesizer, and it bases on a charge-pump PLL topology. The frequency synthesizer can be used for IEEE 802.16b unlicensed band of WiMAX(World Interoperability for Microwave Access) from 5.725GHz to 5.825GHz. It provides the one ration frequency ranged from 5.13GHz to 5.22GHz for the local oscillator in RF front-end circuits. The proposed frequency synthesizer consists of a phase-frequency detector, a charge pump, a low-pass loop filter, a voltage-controlled oscillator, and a pulse-swallow divider. In system design, we present the new architecture for voltage-controlled oscillator to achieve low power consumption and low phase noise. Moreover divider is implemented by an optimal extended true single-phase clock-base prescaler. It can achieve high-resolution frequency operation and reduction of power consumption. This chip is fabricated in a TSMC 0.18μm CMOS 1P6M technology process. The whole chip area is 1.1 mm2.
CHAPTER 1 INTRODUCTION 1
1.1 Motivation 1
1.2 Thesis Organization 4
CHAPTER 2 THE CONCEPTS OF FREQUENCY SYNTHESIZER 5
2.1 RF Front-end Circuit 5
2.1.1 Phase noise, Spurs, and Lock time 6
2.1.2 Specification of frequency synthesizer fot WiMAX 6
2.2 Types of Frequency Synthesizer 8
2.2.1 The Digital Synthesizer 8
2.2.2 The Direct Synthesizer 10
2.2.3 The Indirect Synthesizer 11
2.3 Frequency Synthesizer 12
2.3.1 Basic Concepts 12
2.3.2 Voltage-Controlled Oscillator 13
2.3.3 Phase Frequency Detector (PFD) 17
2.3.4 Charge Pump and Loop Filter 21
2.3.5 Frequency Divider 23
CHAPTER 3 The Proposed Frequency Synthesizer 26
3.1 Introduction 26
3.2 VCO (voltage controlled oscillator) 28
3.2.1 Cross-coupled LC VCO 28
3.2.2 The proposed LC VCO 30
3.3 Frequency Divider 36
3.3.1 High speed prescaler 38
3.3.2 Dual-modulus prescaler 39
3.4 Phase-Frequency Detector 40
3.5 Charge Pump 41
3.6 Loop filter 42
CHAPTER 4 SIMULATION RESULT 43
4.1 RF Model and CMOS process 43
4.2 Simulation of VCO 43
4.2.1 Performance of VCO 46
4.3 Simulation of Frequency divider 47
4.4 Simulation of PFD and CP 51
4.5 Simulation of Frequency Synthesizer 52
4.6 Layout of Chip 60
CHAPTER 5 MEASUREMENT RESULT 61
5.1 Measurement result 61
CHAPTER 6 CONCLUSION AND FUTURE WORK 65
6.1 Conclusion 65
6.2 Future Work 65
Reference 66
[1]WWW.WIMAXFORUM.ORG/HOME
[2]B. Bisla, et al., “RF System and Circuit Challenges for WiMAX,” Intel Technology Journal, vol.8, pp.189-200, Aug. 2004.
[3]C. Samori, S. Levantino, V. Boccuzzi, ”A -94 dBc/Hz@100 kHz, fully-integrated, 5-GHz, CMOS VCO with 18% tuning range for Bluetooth applications,” IEEE Conf. on Custom Integrated Circuits, pp. 201-204, May 2001.
[4]Avanindra Madisetti, Alan Y. Kwentus, and Alan N. Willson, ” A 100-MHZ, 16-b, Direct Digital Frequency Synthesizer with 100-dBc Spurious-Free Dynamic Range,” IEEE J. Solid-state Circuits, Vol. 34, No. 8, pp. 1034-1043, Aug. 1999.
[5]Mozhgan Mansuri, Dean Lin, and Chih-Kong Ken Yang, ” Fast Frequency Acquisition Phase-Frequency Detector for Gsamples/s Phase-Locked Loops,” IEEE J. Solid-state Circuits, Vol. 37, No. 10, pp. 1331-1334, Oct. 2002.
[6]Yijoo Shin, Taewon Kim, Sangwoo Kim, Sungkwon Jang, and Bokki Kim, “A Low Phase Noise Fully Integrated CMOS LC VCO Using a Large Gate Length pMOS Current Source and Bias Filtering Technique for 5-GHz WLAN,” Signals, Systems and Electronics, 2007. ISSSE ''07. International Symposium, pp. 521-524, Aug. 2007.
[7]D.B. Leeson, “A simple model of feedback oscillator noise spectrum,” Proceedings of the IEEE, vol. 54, pp. 329 – 330, 1966.
[8]C. Samori, A.L. Lacaita, F. Villa, F. Zappa, “Spectrum folding and phase noise in LC tuned oscillators,” IEEE Transactions Circuits and Systems, vol. 45, pp.781-790, July 1998.
[9]J. J. Rael and A. A. Abidi, “Physical processes of phase noise in differential LC oscillators,” in Proc. IEEE Custom Integrated Circuits Conf.,Orlando, FL, 2000, pp. 569–572.
[10] E. Hegazi, H. Sjoland, and A. A. Abidi, “A filtering technique to lower LC oscillator phase noise,” IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1921-1950, Dec. 2001.
[11] D. J. Young, S. J. Mallin, and M. Cross, “2 GHz CMOS Voltage-Controlled Oscillator with Optimal Design of Phase Noise and Power Dissipation,” Radio Frequency Integrated Circuits (RFIC) Symposium, 2007 IEEE 3-5 , pp. 131-134, June 2007.
[12]C.C. Boon, M. A. Do, K. S. Yeo, J. G. Ma, and X. L. Zhang, “RF CMOS low-phase-noise LC oscillator through memory reduction tail transistor,” IEEE J. Solid-State Circuits, Vol. 51, pp. 85-90, Feb 2004.
[13]T. Fuse, M. Tokumasu and H. Fujii, “A 1.1V SOI CMOS Frequency using Body-Inputting SCL Circuit Technology,” 2000 IEEE International SOI Conference, pp. 106-107, Oct. 2000.
[14]H. D. Wohlmuth, D. Kehrer and W. Simbiirger, “A High Sensitivity Static 2:1 Frequency Divider up to 19GHz in 120nm CMOS,” 2002 IEEE Radio Frequency Integrated Circuit Symposium, pp.231-234, 2002.
[15]JJ. M. C. Wong, V. S. L. Cheung and C. Luong. “A 1-V 2.5mW 5.2-GHz Frequency Divider in a 0.35-μm CMOS Process,” IEEE Journal of Solid-State Circuits, Vol. 38, NO. 10, pp. 1643-1648, Oct. 2003.
[16]D. J. Yang and K. O. Kenneth, “A 14-GHz 256-257 Dual-Modulus Prescalar with Secondary Feedback and Its Application to a Monolithic CMOS 10.4-GHz Phase-Locked Loop,” IEEE Transactions on Microwave Theory and Techniques, Vol. 52, No. 2, Feb. 2004.
[17]X. P. Yu, M. A. Do, W. M. Lim, K. S. Yeo, and J. G. Ma, “Design and Optimization of the Extended True Single-Phase Clock-Based Prescaler,” Microwave Theory and Techniques, IEEE Transactions, vol. 54, no. 11, pp. 3828-3835, Nov. 2006.
[18]H.-C. Chow, and N.-L. Yeh, “A new phase-locked loop with high speed phase frequency detector,” Circuits and Systems, 2005. 48th Midwest Symposium 7-10, pp. 1342-1345, Aug. 2005.
[19]Chung-Yu Wu, and Chi-Yao Yu, “A 0.8 V 5.9 GHz wide tuning range CMOS VCO using inversion-mode band switching varactors,” IEEE Conf. Circuits and Systems 2005, vol. 5, pp. 5079-5082, May 2005.
[20]Yi-Hsien Cho, Ming-Da Tsai, Ying-Tang Chang, and Huei Wang, “A Wide-band Low Noise Quadrature CMOS VCO,” IEEE Conf. Asian Solid-State Circuits, pp. 325-328, Nov. 2005.
[21]S.-L. Jang, Y.-H. Chuang, Y.-H. S-H. Lee, L.-R. Chi, and C.-F. Lee, “An Integrated 5–2.5-GHz Direct-Injection Locked Quadrature LC VCO,” IEEE J. Microwave and Wireless Components Letters, vol. 17, no. 2, pp. 142-144, Feb. 2007.
[22]Leung, G.C.T.; Luong, H.C.; “A 1-V 5.2-GHz CMOS synthesizer for WLAN applications”, IEEE Journal of Solid-State Circuits, Vol. 39, no 11, pp. 1873-1882 , Nov. 2004.
[23]N. Pavlovic, J. Gosselin and K. Mistry. “ A 10GHz Frequency Synthesizer for 802.11a in 0.18μm CMOS,” Proceeding of the 30th European Solid-State Circuits Conference, pp.367-370, Sept. 2004.
[24]A. Marsolais, M. N. El-Gamal and M. Sawan,”A CMOS Frequency Synthesizer Covering the Lower and Upper Bands of 5GHz WLANs,” Proceeding of the 46th IEEE International Midwest Symposium in Circuit and systems, Vol 3, pp.1146-39, Dec. 2004.
[25]C. Toumazou, G. Moschytz, and B. Gilbert, Trade-offs in analog circuit design: the designer’s companion, Dordrecht, The Nether lands: Kluwer Academic Publisher, 2002.
[26]Robert C. Chang and Lung-Chih Kuo, “A New Low-Voltage Charge Pump Circuit for PLL,” IEEE International Symposium on Circuits and Systems ISCAS, pp.701-703, May 2000
[27]Tord Johnson, Ali Fard, and Denny Aberg, “An Improved Low Voltage Phase-Frequency Detector with Extended Frequency Capability,” Circuits and Systems, 2004. MWSCAS ’04. The 2004 47th Midwest Symposium on Vol. 1, pp. 181-184, July 2004.
[28]Fard, A.; Johnson, T.; Aberg, D.; “A low power wide band CMOS VCO for multi-standard radios”, IEEE Conf. on Radio and Wireless Conference, pp. 79-82, Sept 2004.
[29]Chung-Yu Wu; Chi-Yao Yu; “A 0.8 V 5.9 GHz wide tuning range CMOS VCO using inversion-mode bandswitching varactors”, IEEE Conf. Circuits and Systems, 2005. ISCAS 2005, Vol. 5, pp. 5079-5082, May 2005.
[30]Yi-Hsien Cho; Ming-Da Tsai; Ying-Tang Chang; Huei Wang; “A Wide-band Low Noise Quadrature CMOS VCO”, IEEE Conf. Asian Solid-State Circuits, pp. 325-328, Nov. 2005.
[31]Zhou Zhujin; Li Ning; Li Wei; Ren Junyan; “A Power-Optimized CMOS Quadrature VCO with Wide-Tuning Range for UWB Receivers”, IEEE Conf. Circuits and Systems, 2007. ISCAS 2007, pp. 437-440, May 2007.
[32]Jang, S.-L.; Chuang, Y.-H.; Lee, S.-H.; Chi, L.-R.; Lee, C.-F.; “An Integrated 5–2.5-GHz Direct-Injection Locked Quadrature LC VCO”, IEEE J. Microwave and Wireless Components Letters, Vol. 17, Issue 2, pp. 142-144, Feb. 2007.
[33]Benzard Razavi, “RF MICROELECTRONICS”, PRENTICE HALL PTR, 1998.
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