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研究生:黃威晟
研究生(外文):Wei-Sheng Huang
論文名稱:三維圖形加速系統單晶片之System/RTL/FPGA/Chip均一化驗證方法
論文名稱(外文):A Unified System/RTL/FPGA/Chip Verification Methodology for a 3D Graphics SoC
指導教授:黃英哲黃英哲引用關係
指導教授(外文):Ing-Jer Huang
學位類別:碩士
校院名稱:國立中山大學
系所名稱:資訊工程學系研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:96
語文別:中文
論文頁數:120
中文關鍵詞:三維圖形系統單晶片驗證
外文關鍵詞:3D graphicsVerification methodologySoCUnified
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近年來,在IC設計領域中廣受討論的議題,即是在如何在複雜的SoC環境下進行有效率的驗證,進而提升晶片Tape-out成功的信心程度。而我們在SoC驗證中面對不同抽象層次的驗證環境,如System Modeling Level、Register Transfer Level、FPGA Level以及Chip Level的驗證環境,要如何均一化測試樣本,使其能夠在不同抽象層次的驗證環境也能使用相同的測試樣本進行測試,以讓SoC硬體在不同的驗證環境達到交互驗證的目標,這是我們所面對最主要的課題。因此,本篇論文提出基於三維圖形加速系統單晶片(3D Graphics SoC)之驗證方法為目標,並均一化測試樣本,讓不同抽象層次之驗證環境都能重複使用相同之測試樣本,實現在不同的驗證環境下交互驗證的目標。同時面對3DG SoC龐大的測試樣本,我們也提出一個自動化驗證機制,使得執行模擬以及結果比對不必再透過以人工的方式完成,以增加驗證的效率以及正確率。而透過我們所提出的方法,也在有限的時間內,完整的驗證了三維圖形加速系統單晶片的功能。最後,此論文也透過分享3DG SoC由前段到後段之整合以及驗證經驗,讓大家了解由RTL設計到最後晶片Tape-out以及後續測試的相關流程。
In recent years, a theme for generally discussion in IC design domain is how to do the efficient verification in complex SoC environment and raise the confidence when chip taped-out. But when we face the different abstraction levels of verification environment like the System Modeling Level, Register Transfer Level, FPGA Emulation Level and Chip Level verification environment, how to unifiy test-patterns and makes them can be reused and do mutual-verification in different abstraction level verification environments is our main topic. Therefore, this thesis proposed a verification methodology that based on the 3D graphics SoC and unified the test patterns that let the different abstraction levels of verification environment can use the same test patterns. And to face the exetensive test patterns of 3DG SoC, we also proposed an automatic verification mechanism which can run the simulation and compare the simulation results automatically and improve the verification efficiency. Finally, we also share the 3DG SoC integration and verification experience from front-end to back-end, hope to makes everyone understand the related flow from RTL design to test-chip testing.
Chapter 1. Introduction 1
1. 1 Background 1
1. 2 Motivation 3
1. 3 Research Methodology 5
1. 4 Contribution 6
1. 5 Thesis Architecture 6
Chapter 2. Related Works 7
2. 1 FoCuS Platform 7
2. 2 Complex ASIC Design Verification Methodology 8
Chapter 3. Verification Environments 9
3. 1 System Modeling Level 9
3. 1. 1 Introduction 9
3. 1. 2 Verification Environment Setup 11
3. 2 Register Transfer Level 13
3. 2. 1 Introduction 14
3. 2. 2 Verification Environment Setup 16
3. 3 FPGA Emulation Level 17
3. 3. 1 Introduction 17
3. 3. 2 Verification Environment Setup 20
3. 4 Chip Level 22
3. 4. 1 Introduction 22
3. 4. 2 Verification Environment Setup 27
Chapter 4. 3D Graphics SoC 28
4. 1 3DG SoC Introduction 28
4. 2 3DG SoC Integration 29
4. 2. 1 3DG SoC Architecture 29
4. 2. 2 3DG SoC Interface Definition 33
4. 3 3DG SoC Verification 36
4. 3. 1 3DG SoC Verification Environment 36
4. 3. 2 Test Patterns in 3DG SoC 38
4. 3. 3 Bridge in System Modeling and Register Transfer Level 48
4. 3. 4 Automatic Verification Mechanism 51
4. 4 3DG SoC Test Chip Testing 54
4. 4. 1 Testing Flow 54
4. 4. 2 Test Chip on Agilent SoC Tester 58
4. 4. 3 Test Chip on Versatile 63
Chapter 5. Verification and Testing Results 68
5. 1 Before Tape Out 68
5. 2 After Tape Out 69
Chapter 6. Conclusion 82
Chapter 7. Future Works 83
References 84
Appendix 85
3DG SoC Synthesis Script 85
3DG SoC Registers Definition 100
[1]Ken Albin, “Nuts and Bolts of Core and SOC Verification,” in Proceedings of the Design Automation Conference (DAC), 2000.
[2]AMBA Specification (Rev 2.0),
http://www.arm.com
[3]Hekmatpour, A., Alley, C., Stempel, B., Coulter, J., Salehi, A., Shafie, A., and Palenchar, C., “A Heterogeneous Functional Verification Platform”, in Proceedings of the Custom Integrated Circuits Conference (CICC), 2005, pp. 63-66.
[4]Mansour H. Assaf, Sunil R. Das, Wael Hermas, and Wen –B. Jone, “Promising Complex ASIC Design Verification Methodology”, in Proceedings of the Instrumentation and Measurement Technology Conference (IMTC), 2007, pp. 1-6.
[5]Sasan Iman, Sunita Joshi, “The e-Hardware Verification Language”, May. 2004.
[6]Cai, L., and Gajski, D., “Transaction Level Modeling: an Overview”, in Proceedings of the Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2003, pp.19-24.
[7]CoWare Platform Architect,
http://www.coware.com/products/platformarchitect.php
[8]CoWare ConvergenSC Training Manual, Feb. 2004
[9]Versatile/LT-XC2V4000+ Logic Tile User Guide, Oct. 2007
[10]RealView Platform Baseboard for ARM926EJ-S User Guide, Oct. 2007
[11]Analyzer Tile User Guide, Oct. 2003
[12]ARM, Example AMBA SYstem User Guide ARM DUI0092C, http://infocenter.arm.com/help/topic/com.arm.doc.dui0092c/DUI0092C.pdf
[13]Application Note 119 Implementing AHB Peripherals in Logic Tiles
http://infocenter.arm.com/help/topic/com.arm.doc.dai0119e/AN119_Implementing_AHB_Peripherals_in_Logic_Tiles.pdf
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