臺灣博碩士論文加值系統

根據相關的論文描述, 一個專案在測試驗證的時間佔總時程的大約60˜70%, 再加上現今
產品的生命週期縮短, 因此測試驗證的方法對於能否在計劃的時間內有效率完成, 佔有很重要
的因素。而在針對處理器的驗證方面, 更因為有許多更加強的運算功能, 造成在驗證與條件設
計測試程式時更加困難。
而本論文中是以本實室所發展的一顆以ARM 1022E 架構與V5TE 指令集為基礎的處
理器SYS32TME III, 做為測試驗證的處理器, 在論文中主要是說明處理器的驗證流程, 並配
合實作出可以幫助產生測試程式的工具verification language, 使用者可以利用verification
language 快速的產生testbench 加速驗證的時程, 也利用針對corner case 手寫產生測試
程式, 並且可在不同的驗證環境下重複使用, 最後再使用C 語言撰寫應用程式, 也根據不同的
特性建立了不同的驗證環境, 最後找出處理器、驗證環境、介面轉換電路、指令模擬器的錯誤
並修正電路, 並在電路內部嵌入monitor 藉以提供資訊給驗證者, 可以知道測試程式的功能
驗證涵蓋率。

According to references, testing and verification of a hardware circuit project
occupy about 60%˜70% of project time. Now that product cycle time is decreasing,
verification methodology is an important parameter for effective and successful
completion of a design project. Enhanced processor functions also make verification
conditions more difficult.
In this thesis the processor SYS32IME III, which is constructed based on architecture
of ARM 1022E, is verified by using V5TE instruction set. This thesis
focus on processor verification flow and others to help verification method. The
verification language that is used to help generate testbench are described in this
paper. Also, corner cases are generated, producing test cases that may be reused
in different verification environments. Lastly, errors from CPU architecture, verification
environments, interface wrapper and instruction set simulator were found
in different verification environment and fixed. To conclude the study, insertion
of self-implemented RTL monitor circuit into CPU architecture supply verification
information about testbench’s coverage of functional verification.

1 Introduction 1
1.1 Back ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Research methodology . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.4 Contribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.5 Thesis structural . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Related work 5
2.1 Test program generate method . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Verification method . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2.1 Formal verification . . . . . . . . . . . . . . . . . . . . . . . . 6
Equivalence checking . . . . . . . . . . . . . . . . . . . . . . . 6
Model checking (assertions) . . . . . . . . . . . . . . . . . . . 8
2.2.2 Simulation base . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Instruction set model . . . . . . . . . . . . . . . . . . . . . . . 10
Test template language . . . . . . . . . . . . . . . . . . . . . . 11
Functional fault model . . . . . . . . . . . . . . . . . . . . . . 15
2.2.3 ATPG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3 Verification environment in different stages . . . . . . . . . . . . . . . 19
2.3.1 Direct test (Deterministic) Test . . . . . . . . . . . . . . . . . 19
2.3.2 Tightly couple memory bus system . . . . . . . . . . . . . . . 20
2.3.3 On-chip bus base system . . . . . . . . . . . . . . . . . . . . . 20
2.3.4 FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3 Research methodology 22
3.1 RTL syntax and style checking . . . . . . . . . . . . . . . . . . . . . . 23
3.1.1 Linting check . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2 RTL module verification . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.2.1 Component function verification . . . . . . . . . . . . . . . . . 25
3.2.2 System function verification . . . . . . . . . . . . . . . . . . . 26
Directed testing . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Random testing . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.3 Verification language . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.3.1 Instruction set format: . . . . . . . . . . . . . . . . . . . . . . 31
3.3.2 Testbench describe file: . . . . . . . . . . . . . . . . . . . . . . 47
3.4 Simulation environment . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.4.1 Tightly couple memory bus . . . . . . . . . . . . . . . . . . . 57
3.4.2 On-chip bus base system . . . . . . . . . . . . . . . . . . . . . 58
3.5 Verification environment . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.6 Verification coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.6.1 Code coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.6.2 Functional coverage . . . . . . . . . . . . . . . . . . . . . . . . 63
3.6.3 Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
4 Bug found and fix 70
4.1 Verification plan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4.2 Classify bug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4.3 Bug found and fix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
4.3.1 nLint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Coding style . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
4.3.2 Tightly couple memory bus . . . . . . . . . . . . . . . . . . . 77
Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Wrapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
4.3.3 On-chip bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Wrapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Miss understand Spec. . . . . . . . . . . . . . . . . . . . . . . 93
5 Conclusion 94
6 Future work 95
A Appendix 96
A.1 SYS32TME III architecture . . . . . . . . . . . . . . . . . . . . . . . 96
A.2 SYS32TEM-III project file usage description . . . . . . . . . . . . . . 102
A.3 Testbench file usage description . . . . . . . . . . . . . . . . . . . . . 106
A.4 Testbench generator project file usage description . . . . . . . . . . . 107
A.5 How to get the golden pattern in ADS . . . . . . . . . . . . . . . . . 108
A.6 EASY environment file usage description . . . . . . . . . . . . . . . . 108
A.7 SVN file usage description . . . . . . . . . . . . . . . . . . . . . . . . 113
A.8 Implementation hardware experience . . . . . . . . . . . . . . . . . . 114
A.8.1 Important debug information wire . . . . . . . . . . . . . . . 114
A.8.2 Every important function block and wire description . . . . . 117
Fetch instruction and data rule . . . . . . . . . . . . . . . . . 121
A.9 Design compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
A.9.1 Start Design compiler library path setup . . . . . . . . . . . . 144
A.9.2 Synthesis script . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Reference 152

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