臺灣博碩士論文加值系統

VLSI製程的進步使得外在環境的干擾更容易影響微控器的運作，現在的設計不只追求速度與效能，也開始研究各種容錯(fault-tolerant)技術以提升可靠度及安全性。為開發符合市場導向之容錯微控器。本論文以ARM 9相容指令集雙核心處理器為基礎，設計具容錯技術的強韌型微控器(Robust Micro-Control Unit : RMCU)。強韌型微控器的容錯機制分為兩種運作模式:同步模式(Synchronize mode)及處理器測試模式(Processor test mode)。在同步模式下藉由兩個處理器同時執行同一程式的比較結果偵測其中一個處理器所發生的暫時性錯誤(transient fault)，當暫時性錯誤發生，兩個處理器將使用指令重試(instruction retry)機制進行系統的回復。若同一位址的指令重試次數大於設定值則視為永久性錯誤(permanent fault)，系統將進入處理器測試模式進行雙核心處理器的功能性測試，依照測試結果關閉錯誤處理器並使系統回復正常運作。此作法解決傳統雙核心處理器容錯架構無法修正永久性錯誤的限制，提升雙核心處理器之容錯能力。除了容錯機制的設計外，為提升軟硬體的驗證及開發本論文設計了強韌型微控器之除錯平台。此除錯平台包括強韌型微控器內部以JTAG為基礎的OCD (On-Chip Debugging)單元以及除錯介面程式，除了提供讀寫暫存器及記憶體、設定Breakpoint、Watchpoint以及單步執行外增加了主動插入External Interrupt功能，提供更有效的ISR (Interrupt Service Routine)除錯。在論文的最後我們使用FPGA實現強韌型微控器容錯機制及除錯平台，經過模擬與測試後證實了強韌型微控器之可行性。

With the progress in VLSI technology, the external environment makes it easier for the interference affected the operation of microcontroller. The design of the recently microcontroller, not only the pursuit of speed and performance, also began the study of the various fault-tolerant technology to enhance the reliability and safety. This thesis, being designed for the Fault-tolerant microcontroller according market, presents a Robust Micro-Control Unit : RMCU for dual core architecture of ARM9 ISA.
The RMCU provides two operation modes: synchronize mode and Processor test mode for fault-tolerant mechanism. In synchronize mode, both processors are executing the same program concurrently. The results generated by processors are compared, and every mismatch indicates a transient fault in one of the two processors. When the transient fault occurred, the two processors will use Instruction retry mechanism, recover system operation. If the same address''s errors larger than the number of settings are considered permanent fault, processors will be held, and entered the processor test mode for processor functional test. In accordance with the test results to close the wrong processor and operating system back to normal. This approach to solve the traditional dual-core processor fault-tolerant architecture that can not be fixed to permanent-fault restrictions.
In addition to the design of fault-tolerance mechanism, for the upgrading of software and hardware development and validation of this paper design of the RMCU debug platform. RMCU debug platform including JTAG-based OCD (On-Chip Debugging) unit, and debug interface program. In addition to providing read and write registers and memory, set Breakpoint, Watchpoint and single-step but also take the initiative to increase the external interrupt inserted to provide a more effective ISR (Interrupt Service Routine) debug. In the last of the thesis, we use the FPGA Implementation of the RMCU fault-tolerant mechanisms and debug platform. After simulation and testing, the results prove the feasibility of RMCU.

摘要................................................i
ABSTRACT .........................................iii
目錄................................................v
圖片列表..........................................vii
表格列表...........................................ix
第一章 簡介.........................................1
1-1 研究動機........................................1
1-2 研究目的........................................2
1-3 論文架構........................................2
第二章 相關研究.....................................3
2-1 錯誤類型........................................3
2-2 常見的容錯處理器................................4
2-2-1 TMR processor ................................4
2-2-2 Fault-tolerant for VLIW processor.............5
2-2-3 IBM Power6 Microprocessor ....................6
2-2-4 Instruction retry for Dual-core processor.....7
2-3 容錯處理器之分析與討論..........................8
2-4 自我測試........................................9
2-4-1 Built-In Self-Test............................9
2-4-2 Software-Based Self-Testing..................10
2-5 除錯平台介紹...................................11
2-5-1 OCD..........................................11
2-5-2 JTAG.........................................12
2-5-3 除錯平台功能.................................20
第三章 強韌型微控器容錯機制之設計..................22
3-1 ARM 9 處理器架構...............................22
3-2 強韌微控器容錯架構.............................24
3-3 強韌微控器容錯機制的運作模式...................25
3-3-1 Synchronize mode ............................25
3-3-2 Processor test mode .........................27
3-4 指令重試機制...................................29
3-4-1 Instruction retry unit.......................29
3-4-2 處理器的比較.................................30
3-4-3 影響指令重試的指令...........................33
3-5 處理器測試機制.................................39
3-5-1 Processor test unit..........................40
3-5-2 Register test ...............................42
3-5-3 Datapath test ...............................45
3-6 External Interrupt 錯誤機制....................47
第四章 支援軟體除錯之架構設計......................49
4-1 強韌型微控器之除錯架構.........................49
4-2 OCD unit.......................................50
4-2-1 Control unit.................................52
4-2-2 BWI unit ....................................54
4-2-2 RF_RW unit...................................56
4-3 OCD 運作流程...................................57
4-3-1 讀寫處理器內部暫存器以及記憶體...............57
4-3-2 設定Breakpoint ..............................58
4-3-3 設定Watchpoint...............................60
4-3-3 單步執行.....................................64
4-3-4 插入External Interrupt ......................64
第五章 模擬與測試..................................66
5-1 強韌型微控器之合成結果.........................66
5-2 強韌型微控器容錯架構之模擬測試.................67
5-2-1 指令重試模擬測試與分析.......................68
5-2-2 處理器測試模擬測試與分析.....................72
5-3 強韌型微控器除錯平台之測試.....................79
第六章 結論........................................83
參考文獻...........................................84
附錄...............................................88

[1] T. Karnik, P. Hazucha, and J. Patel, “Characterization of Soft Errors Caused by Single Event Upsets in CMOS Processes”, IEEE Trans. Dependable and Secure Computing, April-June 2004, Vol. 1, No. 2, pp. 128-143
[2] P. Shivakumar et al., “Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic,” DSN, 2002, pp. 389-398
[3] E. Dupont, M. Nicolaidis, and P. Rohr, Embedded Robustness IPs for Transient-Error-Free IC''s, IEEE Design & Test of Computers, May–June 2002.
[4] Tat Ngai, Earl E. Swartzlander Jr., Chen He: Enhanced Concurrent Error Correcting Arithmetic Unit Design Using Alternating Logic. DFT 2001, pp.78-83
[5] E Touloupis, J A Flint, V A Chouliaras and D Ward, ‘A TMR processor architecture for safety-critical automotive applications’, Proceedings of IEE/ACM Postgraduate Seminar on Soc Design, Test and Technology , IEE , Loughborough University UK, 15th September 2004
[6] Touloupis, E., Flint, J. A. and Chouliaras, V. A., ‘A Fault-Tolerant Architecture for Automotive Applications’ , Proceedings of PREP 2004, EPSRC, University of Hertfordshire UK, April 2004, 2004, 90-91.
[7] Y. Y. Chen, S. J. Horng, H. C. Lai, “An integrated fault-tolerant design framework for VLIW processors, ”18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’03), Boston, Massachusetts, Nov. 3-5, 2003, pp. 555-562.
[8] Y. Y. Chen, “Incorporating Fault-Tolerant Features in VLIW Processors, ”International Journal of RELIABILITY, QUALITY AND SAFETYENGINEERING, pp. 397-409, OCT 2005.
[9] Soohong P. Kim, Raymond R. Hoare, and Henry G. Dietz, “VLIW Across Multiple Superscalar Processors On A Single Chip,” International Conference on Parallel Architectures and Compilation Techniques, pp. 166 -175, Nov. 1997.
[10] Kevin Reick, Pia N. Sanda, Scott Swaney, Jeffrey W. Kellington, Michael Floyd, “Fault-Tolerant Design of the IBM POWER6 Microprocessor,” http://www.hotchips.org/archives/hc19/2_Mon/HC19.01/HC19.01.01.pdf
[11] J. Fredrich, B. McCredie, N. James, B. Huott, B. Curran, E. Fluhr, G. Mittal, et al., “Design of the POWER6 Microprocessor,” Proceedings of the IEEE International Solid-State Circuits Conference, Digest of Technical Papers, San Francisco, CA, 2007, pp. 96–97.
[12] T. Kottke and A. Steininger, “A generic dual core architecture,” In 7th IEEE Workshop on Design andDiagnostics of Electronic Circuits and Systems, pages 159–166, 2004.
[13] Christian El Salloum, Andreas Steininger, Peter Tummeltshammer, Werner Harter, “ Recovery Mechanisms for Dual Core Architectures,” DFT 2006: 380-388
[14] L. Chen and S. Dey, “Software-Based Self-Testing Methodology for Processor Cores,” IEEE Transactions on CAD of Integrated Circuits and Systems, vo.20, no.3, March 2001, pp. 369-380.
[15] N. Kranitis, A. Paschalis, D. Gizopoulos, and G. Xenoulis, “Software-based self-testing of embedded processors”, IEEE Transactions on Computers, vol.54(4), pp. 461-475, April 2005
[16] C. H. Chen, C. K. Wei, T. H. Lu, and H.W. Gao, “Software-Based Self-Testing With Multiple-Level Abstractions for Soft Processor Cores,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.15, no.5, May 2007, pp.505 – 517.
[17] G. Xenoulis, D. Gizopoulos, N. Kranitis, and A. Paschalis, “Low-cost, on-line software-based self-testing of embedded processor cores,” 9th IEEE On-Line Testing Symposium, July 2003, pp.149 – 154.
[18] A. Paschali and D. Gizopoulos, “Effective　software-based　self-test　strategies for on-line periodic testing of embedded　processors,”　IEEE　Transactions on Computer-Aided Design of Integrated Circuits and　Systems, pages 88-99, 2005
[19] Optimal Periodic Testing of Intermittent Faults in Embedded Pipelined Processor Applications, N.Kranitis, A.Merentitis, N.Laoutaris, G.Theodorou, A.Paschalis, D.Gizopoulos, C.Halatsis, in Proceedings of the IEEE Design Automation and Test in Europe Conference (DATE2006), Munich, Germany, March 2006.
[20] IEEE Standard Test Access Port and Boundary-Scan Architecture,The Institute of Electrical and Electronics Engineers, Inc, Feb. 2001
[21] ARM9TDMI Technical Reference Manual, Rev. 3, ARM Inc, 2000
[22] MPLAB ICD2 In-Circuit Debugger User’s Guide, Microchip. Technology Inc, 2003
[23] O. Schliebusch and D. Kammler and A. Chattopadhyay and R. Leupers and G. Ascheid and H. Meyr, “Automatic generation of JTAG interface and debug mechanism for ASIPs”, GSPx, 2004
[24] I. J. Huang, C. F. Kao, H. M. Chen, J. N. Ruan and T. A. Lu, "A Retargetable Embedded In-Circuit Emulation Module for Microprocessors," IEEE Design and Test of Computers, July/August 2002, pp. 28-38
[25] Jih-Ching Chiu and Yu-Liang Chou,"Compact Dual-Core Architecture, "The 18th VLSI Design/CAD Symposium, pp. 692-695, Aug. 2007.
[26] Yang Liu Wang-Hua Wu Xiao-Fang Zhou Dian Zhou, “ A Novel On-chip Debug System with Quick All-registers Scan Chain Based on JTAG”, Solid-State and Integrated Circuit Technology, 2006, pp. 1941 – 1943