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研究生:林正大
研究生(外文):Jeng-Da Lin
論文名稱:具有源/汲極縛點之底部閘極薄膜電晶體之模擬與製作
論文名稱(外文):Simulation and Fabrication of the Bottom Gate TFT with Source/Drain Tie
指導教授:林吉聰
指導教授(外文):Jyi-Tsong Lin
學位類別:碩士
校院名稱:國立中山大學
系所名稱:電機工程學系研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:96
語文別:中文
論文頁數:71
中文關鍵詞:薄膜電晶體
外文關鍵詞:TFT
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在本論文中,我們製作出一種具有源極/汲極縛點(S/D-tie) 之底部閘極(bottom gate) 薄膜電晶體元件。傳統的底部閘極元件,因為絕緣埋氧化層完全阻隔,使得通道中產生的熱無法散出,導致有嚴重的自體加熱效應(self-heating effect),這些不理想之因素將導致元件可靠度(reliability)下降。為了改善自體加熱效應,我們提出一個新的非典型架構,叫做具有源極/汲極縛點之底部閘極薄膜電晶體元件來增加元件穩定性。而且源極/汲極縛點底部閘極元件同時具有部份空乏型矽覆絕緣場效電晶體(PD SOI)和全空乏型矽覆絕緣場效電晶體(FD SOI)的優點,包括減少源/汲極串接電阻並且不會產生浮體效應(Floating body effect)。此外,我們在底部閘極元件兩旁形成適當厚度的邊襯(spacer),讓源、汲極不要靠得太近,可以減少米勒電容效應(Miller’s capacitance effect)。

根據ISE TCAD 10.0 模擬發現,源極/汲極縛點(S/D-tie) 之底部閘極薄膜電晶體元件,其輸出曲線IDS - VDS沒有負微分電阻的效應,主要原因它具有源極/汲極縛點,所以能夠有效紓緩載子在通道中所衍生出來的“自體加熱效應”,改善熱所導致的不穩定性;而且它也能夠抑制短通道效應。
In this thesis, a bottom gate TFT with source/drain tied (S/D-tied) device is realized.
Because the conventional bottom gate device has serious “self-heating effect”due to the burrier-oxide insulator, the heat produced in the channel is unable to disperse. These non-idea effects will decrease device reliability. In order to improve this self-heating effect for the conventional bottom-gate device, we present a new non-classical architecture called the bottom gate TFT with S/D-tied to achieve enhanced device reliability. In addition, this bottom-gate MOSFET with source/drain tied (S/D-tied) device has the advantages inherently possessed by partially depleted
and fully depleted silicon on insulator device. It includes not only the decreases of the source/drain series resistance but also the free of the floating body effect. Besides, to reduce Miller’s capacitance effect we formed an enough-thickness spacers at both sides of the bottom gate and let the source and the drain region do not close nearly.Because the conventional bottom gate device has serious “self-heating effect”due to the burrier-oxide insulator, the heat produced in the channel is unable to disperse. These non-idea effects will decrease device reliability. In order to improve this self-heating effect for the conventional bottom-gate device, we present a new
non-classical architecture called the bottom gate TFT
with S/D-tied to achieve enhanced device reliability. In addition, this bottom-gate MOSFET with source/drain
tied (S/D-tied) device has the advantages inherently
possessed by partially depleted and fully depleted silicon on insulator device. It includes not only the decreases of the source/drain series resistance but also the free of the floating body effect. Besides, to reduce Miller’s capacitance effect we formed an enough-thickness spacers at both sides of the
bottom gate and let the source and the drain region do not close nearly.
目錄
第一章 導 論..............................................................................................................1
1-1 背景............................................................1
1-2 動機............................................................1
第二章 新元件的設計與實作......................................................................................8
2-1 元件的設計......................................................8
2-2 元件的實作.....................................................13
第三章 結果與討論....................................................................................................15
3-1 本體(Body)用單晶矽的情況之模擬結果與討論.......................15
3-1-1 自體加熱效應 (self-heating effect)的比較.....................................15
3-1-2 比較短通道效應(short channel effect;SCEs)................................19
3-2.本體(Body)用多晶矽之模擬結果與討論.............................23
3-2-1 自體加熱效應 (self-heating effect)的比較.....................................23
3-2-2 浮體效應(Floating effect).................................................................26
3-2-3 比較短通道效應(short channel effect;SCEs)................................30
3-3.實作之結果.....................................................32
3-3.總結...........................................................40
第四章 結論與未來發展............................................................................................42
4-1 結論.......................................................................................................................42
4-2 未來發展..............................................................................................................42
參考文獻: ....................................................................................................................45
附錄..............................................................................................................................49
附錄A. 具有源/汲極縛點之底部閘極之Runcard 步驟:..................49
附錄B.發表的會議論文..............................................63

圖目錄
圖1.1.(a). UTB SOI架構圖 (b).E-S/D架構圖--------------------------2
圖1.2. Recessed Source Drain Ultra-thin Body SOI MOSFET 架構圖----------3
圖1.3. T-Shaped Body SOI MOSFET架構圖------------------------------3
圖1.4. Self-Aligned Bottom-Gate MOS Transistor--------------------------4
圖1.5. bFDSOI架構圖------------------------------------------------4
圖1.6.(a).A PUSD PiFET (b).A PUC PiFET架構圖-----------------------5
圖1.7. quasi-SOI MOSFET structure with S/D surrounded by insulator架構-------5
圖1.8.(a).One side SBT (b). Two-side SBT--------------------------------- 6
圖1.9.bSPIFET架構圖-------------------------------------------------6
圖1.10. 本論文提出的新的架構;S/D-tied BG TFT-------------------------7
圖2.1. (a). a S/D-tied BG TFT (b). a conventional BG TFT 之本體(Body)用單晶矽
的情況架構----------------------------------------------------------9
圖2.2. S/D-tied BG TFT 之本體(Body)用單晶矽的情況主要製程模擬步驟---- 11
圖2.3.(a). a S/D-tied BG TFT (b). a conventional BG TFT之本體(Body)用多晶矽的
架構圖-------------------------------------------------------------11
圖2.4. the S/D-tied BG TFT之本體(Body)用多晶矽的主要模擬步驟---------- 13
圖2.5. S/D-tied BG TFT實作製程之重要流程步驟 ------------------------14
圖3.1. S/D-tied BG TFT和傳統BG TFT 在LG為30nm 時的撞擊游離比較圖(a).
S/D-tied BG TFT在VGT = 1.0 V. (b). 傳統BG TFT 在VGT = 1.0 V------------16
圖3.2. S/D-tied BG TFT和傳統 BG TFT在LG為30nm 時的電洞溫度(ok)比較圖
(a).S/D-tied BG TFT在VGT = 1.0 V (b). 傳統BG TFT在VGT = 1.0 V ----------17
圖3.3. S/D-tied BG TFT和傳統 BG TFT在LG為30nm 時的晶格溫度(ok)比較圖
(a).S/D-tied BG TFT在VGT = 1.0 V (b). 傳統BG TFT在VGT = 1.0 V----------18
圖3.4. 模擬S/D-tied BG 和傳統BG TFT之IDS - VDS圖---------------------19
圖3.5. S/D-tied BG 和傳統BG TFT 在LG = 30 nm 沿著通道時的電子速度比較
圖-----------------------------------------------------------------19
圖3.6.不同通道長度(LG)的臨界電壓roll-off和次臨界擺幅比較圖------------20
圖3.7.不同通道長度(LG)的DIBL比較圖---------------------------------20
圖3.8. S/D-tied BG 和傳統BG TFT 在不同本體(Body)厚度對臨界電壓比較圖
------------------------------------------------------------ ------ 21
圖3.9. S/D-tied BG和傳統BG TFT在不同本體(Body)厚度對次臨界擺幅比較圖
-------------------------------------------------------------------21
圖3.10. S/D-tied BG 和傳統BG TFT在不同本體(Body)厚度對DIBL比較圖
-------------------------------------------------------------------22
圖3.11. S/D-tied BG 和傳統BG TFT的ION與IOFF比較圖-------------- ----22
圖3.12. S/D-tied BG 和傳統BG TFT在LG = 1000nm時,本體(Body)厚度為25nm
時晶格溫度(oK)比較圖.(a).S/D-tied BG在LG = 1.5 V (b).傳統BG TFT 在VGT =
1.5 V. --------------------------------------------------------------23
圖3.13. S/D-tied BG TFT和傳統BG TFT 在LG = 1000nm,本體(Body)厚度為
100nm 時的電洞溫度(ok)比較圖. (a). S/D-tied BG TFT 在VGT = 1.5 V (b).傳統BG
TFT在VGT = 1.5-----------------------------------------------------25
圖3.14. S/D-tied BG TFT和傳統BG TFT在LG = 1000nm,本體(Body)厚度為50nm
時的撞擊游離比較圖(a).S/D-tied BG TFT在VGT = 1.5 V (b).傳統BG TFT在VGT =
1.5 V---------------------------------------------------------------26
圖3. 15. PD SOI元件發生碰撞游離(impact ionization)時,受閘極電場影響,電洞
被推到假中性區示意圖(以NMOS 為例)。-------------------------------26
圖3. 16.使用ISE TCAD 10.0 模擬兩種不同載子之濃度分佈(a)電洞電流密度方向
(b)電子電流密度方向。----------------------------------------------28
圖3.17. 使用ISE TCAD 10.0模擬全部載子之濃度分佈圖。------------------28
圖3.18. 兩個架構的輸出曲線比較圖。-----------------------------------29
圖3.19. 傳統底部閘極元件改變本體(Body)厚度的輸出曲線比較圖。---------29
圖3.20. 具有源/汲極縛點底部閘極元件改變本體(Body)厚度的輸出曲線比較
圖。----------------------------------------------------------------30
圖3. 21. S/D-tied BG和傳統 BG TFT 不同本體(Body)厚度對臨界電壓比較圖. -30
圖3.22. S/D-tied BG 和傳統BG TFT在不同本體(Body)厚度對次臨界擺幅比較圖.
-------------------------------------------------------------------31
圖3.23. S/D-tied BG 和傳統BG TFT在不同本體(Body)厚度對DIBL比較圖---32
圖3.24. L-edit 之S/D-tied BG TFT光罩圖--------------------------------32
圖3.25. 元件製作流程圖: (a)、(b)、(c) 分別為蝕刻後In-Line SEM檢視之Bottom
Gate 之線寬8um、4um、2um、1um. ------------------------------------33
圖3.26.In-Line SEM 檢視之Well region Pattern 之線寬8.4um、4.4、2.4、1.4um.
-------------------------------------------------------------------34
圖3.27.In-Line SEM 檢視之Action region Pattern-------------------------35
圖3.28.In-Line SEM檢視之Metal region Pattern--------------------------36
圖3.29.新架構(S/D-tied BG TFT)的熱場發射掃描式電子顯微鏡(TFESEM)元件
剖面圖
。-------------------------------------------------
36
圖3.30.傳統架構(Conv. BG TFT)的熱場發射掃描式電子顯微鏡(TFESEM)元件剖
面圖。--------------------------------------------------------------37
圖3.31. 為HP4156量測時之簡圖--------------------------------------37
圖3.32. 傳統底部閘極元件之輸入曲線IDS - VGS實驗量測圖。--------------38
圖3.33. 傳統底部閘極元件之輸入曲線Log(IDS )- VGS實驗量測圖。----------38
圖3.34. 傳統底部閘極元件之輸出曲線 IDS - VDS實驗量測圖-------------- 39
圖3.35. 新架構底部閘極元件之輸入曲線IDS - VGS實驗量測圖。------------39
圖3.36. 新架構底部閘極元件之輸入曲線Log(IDS )- VGS實驗量測圖。--------39
圖3.37. 新架構底部閘極元件之輸出曲線 IDS - VDS實驗量測圖------------ 40
圖4.1. S/D-tied Double Gate TFT架構圖--------------------------------43
圖4.2. S/D-tied Double Gate TFT之主要製程步驟流程模擬圖--------------44
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