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研究生:林高正
研究生(外文):Kao-cheng Lin
論文名稱:為抑制短通道效應和改善熱不穩定度之具有內部阻絕層新金氧半電晶體
論文名稱(外文):Novel MOSFETs with Internal Block Layers for Suppressing Short Channel Effects and Improving Thermal Instability
指導教授:林吉聰
指導教授(外文):Jyi-Tsong Lin
學位類別:碩士
校院名稱:國立中山大學
系所名稱:電機工程學系研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:96
語文別:中文
論文頁數:79
中文關鍵詞:阻絕層電晶體熱不穩定度短通道效應
外文關鍵詞:thermal instabilityblock layerMOSFETshort channel effect
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在本論文中,提出數個新金氧半場效電晶體元件:具有L形內部阻絕層的垂直式金氧半電晶體(bVMOS)、具有自我對準內部阻絕層的平面金氧半電晶體(bMOS)、和具有自我對準內部阻絕層的矽鍺金氧半電晶體(bSGMOS)。我們使用側壁Spacer以及回蝕刻的技術形成bVMOS中的L型內部阻絕層,它們可以抑制短通道效應、降低源╱汲極與基體間P-N接面所造成的寄生電容與漏電流,也提供撞擊游離所產生的載子與熱能一個逸散路徑,改善了浮體效應與自我加熱效應。此外,我們利用閘極上方的氮化矽覆蓋層作為硬光罩,以自我對準以及側壁Spacer的方式在通道兩側下方形成內部阻絕層製作bMOS,它能阻隔大部分源╱汲極與本體間的空乏區,抑制短通道效應且增加閘極對通道的控制能力,不僅保有內部阻絕層的特色並改善bVMOS的短處。經由模擬軟體驗證得知內部阻絕層可有效抑制超短通道效應與改善熱不穩定度。最後,我們結合磊晶矽鍺薄膜製程(bSGMOS)在源╱汲極區成長矽鍺薄膜,利用應力提升元件電流驅動力,並將元件性能速度再次提升。
In this paper, several new MOSFET devices, vertical MOSFET with L-shaped internal block layers (bVMOS), planar MOSFET with self-aligned internal block layers (bMOS), and Silicon-Germanium MOSFET with self-aligned internal block layers (bSGMOS) are presented. We use the sidewall spacer and etch back techniques to form the L-shaped internal block layers of bVMOS. They can suppress the short channel effects, diminish the parasitic capacitance, and reduce the leakage current cause by P-N junction between source/drain and body regions. They also provide a pass way to eliminate carriers and heat which generated by impact ionization resulting in suppression of floating-body effect and self-heating effect. In addition, we use Si3N4 cap layer upon gate as a hard mask, combining self-aligned and sidewall spacer techniques to fabricate the internal block layers under the both sides of channel end to form bMOS. The depleted region between source/drain and body is shielded and so the short channel effects and the controllability of gate to channel are improved. The internal block layers not only maintain the character of internal block layers but also ameliorate the drawback of bVMOS. The ISE TCAD simulation results show the short channel effect is suppressed and the thermal instability is improved by the internal block layers effectively in each device. Furthermore, we employ the epitaxial silicon-germanium thin film process (bSGMOS) to form silicon-germanium thin film at source/drain region to improve the device current drive by the strain thereby enhancing the device performance.
目錄
頁數
第一章 導論 -------------------------------------------------- 1
第二章 元件設計與製造 ---------------------------------------- 10
2-1元件設計 ------------------------------------------ 10
2-1-1 bVMOS元件設計與結構 -------------------------- 10
2-1-2 bMOS元件設計與結構 --------------------------- 11
2-1-3 bSGMOS元件設計與結構 ------------------------- 12
2-2 理想製程流程 -------------------------------------- 13
2-2-1 N-type bVMOS --------------------------------- 13
2-2-2 N-type bMOS ----------------------------------- 14
2-3 實際製程 ------------------------------------------ 16
2-3-1 P-type bSGMOS之實際製程 ---------------------- 16
第三章 結果與討論 -------------------------------------------- 17
3-1 模擬結果 ------------------------------------------ 17
3-1-1 N-type bVMOS模擬結果與探討 ------------------- 17
3-1-2 N-type bMOS模擬結果與探討 -------------------- 23
3-2 P-type bSGMOS實作結果 ---------------------------- 38
3-3 討論 ---------------------------------------------- 40
第四章 結論 -------------------------------------------------- 41
第五章 未來發展 ---------------------------------------------- 43
參考文獻 ----------------------------------------------------- 44
附錄 :
A. bSGMOS Runcard ------------------------------------- 51
A-1 製作零層 ---------------------------------------- 51
A-2 定義主動區 -------------------------------------- 53
A-3 閘極圖案的形成 ---------------------------------- 56
A-4 內部阻絕層製作及源極與汲極的形成 ---------------- 59
A-5 製作接觸窗口(Contact Hole) --------------------- 62
A-6 製作金屬層 -------------------------------------- 63
B. 著作列表及全文 ------------------------------------- 64

圖目錄
頁數
圖 1.1:PiFET之結構示意圖。 --------------------------------- 3
圖 1.2:DSOI之結構示意圖。 ---------------------------------- 3
圖 1.3:T-shaped body PD SOI之結構示意圖。 ------------------ 4
圖 1.4:P-Channel FinFET之結構示意圖。 ---------------------- 5
圖 1.5:bVMOS之結構示意圖。 --------------------------------- 5
圖 1.6:Silicon–Carbon Source/Drain之結構示意圖。 ---------- 7
圖 1.7:SPT與DSL技術結合之結構示意圖。 --------------------- 8
圖 1.8:bMOS與bSGMOS之結構示意圖。(a)bMOS,(b)bSGMOS。 ----- 9
圖 2.1.1:bVMOS的元件結構示意圖。 --------------------------- 10
圖 2.1.2:bMOS的元件結構示意圖。 ---------------------------- 11
圖 2.1.3:bSGMOS的元件結構示意圖。 -------------------------- 12
圖 2.2.1:bVMOS之製作流程圖。 ------------------------------- 14
圖 2.2.2:bMOS之製作流程圖。 -------------------------------- 15
圖 3.1.1:bVMOS與對照元件組之結構剖面圖。 ------------------- 17
圖 3.1.2:bVMOS與對照元件組的輸入特性曲線 ------------------- 18
圖 3.1.3:bVMOS與對照元件組的臨限電壓特性圖。 --------------- 19
圖 3.1.4:bVMOS與對照元件組的次臨界曲線特性圖。 ------------- 19
圖 3.1.5:bVMOS與對照元件組的DIBL特性圖。 ------------------ 20
圖 3.1.6:bVMOS與對照元件組的汲極厚度特性圖,(a)DIBL、(b)SS。 21
圖 3.1.7:bVMOS與對照元件組的汲極厚度對VT特性圖。 ----------- 22
圖 3.1.8:bVMOS與對照元件組的輸出特性曲線。 ----------------- 23
圖 3.1.9:bMOS與對照元件組之結構剖面圖。---------------------- 24
圖 3.1.10:bMOS與對照元件之VT - LG特性曲線。------------------- 25
圖 3.1.11:bMOS與對照元件之IDS - VGS特性曲線。----------------- 26
圖 3.1.12:bMOS與對照元件之SS - LG特性曲線。 ---------------- 27
圖 3.1.13:bMOS與對照元件之DIBL - LG特性曲線。 -------------- 28
圖 3.1.14:DIBL値對阻絕層位置分佈圖。 ----------------------- 29
圖 3.1.15:bulk Si元件晶格溫度分佈圖,VGT=1V,VDS=1.25V。 ---- 30
圖 3.1.16:UTBSOI元件晶格溫度分佈圖,VGT=1V,VDS=1.25V。 ----- 31
圖 3.1.17:bMOS元件晶格溫度分佈圖,VGT=1V,VDS=1.25V。 ------- 31
圖 3.1.18:bMOS與對照元件之載子移動率對於位置圖。 ----------- 32
圖 3.1.19:bMOS與對照元件之源╱汲極串接電阻對於LG的特性曲線。 33
圖 3.1.20:bMOS與對照元件之IOFF對於ION特性曲線。 ------------ 34
圖 3.1.21:bMOS與對照元件之gm對於LG特性曲線。 -------------- 35
圖 3.1.22:bMOS與對照元件之輸出特性曲線。 -------------------- 36
圖 3.1.23:bMOS與對照元件之C-V特性曲線。 -------------------- 37
圖 3.1.24:bMOS與對照元件之Delay time對於LG特性曲線。 ------ 37
圖 3.2.1:P-type bSGMOS之主動區SEM圖。----------------------- 38
圖 3.2.2:P-type bSGMOS之bSGMOS之閘極區SEM圖。-------------- 39
圖 3.2.1:P-type bSGMOS之Metal Contact SEM圖。--------------- 39
圖 A.1元件製程示意圖:乾氧化pad oxide及LPCVD Si3N4。 ------- A-3
圖 A.2元件製程示意圖:負光阻旋轉塗佈。 ---------------------- A-4
圖 A.3元件製程示意圖:曝光後顯影。 -------------------------- A-4
圖 A.4 元件製程示意圖:乾蝕刻氮化矽以及二氧化矽。 ----------- A-5
圖 A.5 元件製程示意圖:蝕刻後光阻去除。 --------------------- A-5
圖 A.6 元件製程示意圖:LOCOS後乾蝕刻氮化矽以及二氧化矽。 ----- A-6
圖 A.7 元件製程示意圖:離子佈植。 --------------------------- A-6
圖 A.8 元件製程示意圖:沉積gate oxide、Poly gate、nitride。 -- A-7
圖 A.9 元件製程示意圖:閘極區曝光後顯影。 ------------------- A-7
圖 A.10 元件製程示意圖:閘極區域的定義。 -------------------- A-8
圖 A.11 元件製程示意圖:沉積氮化矽。 ------------------------ A-8
圖 A.12 元件製程示意圖:乾蝕刻氮化矽,用以保護閘極。 -------- A-8
圖 A.13 元件製程示意圖:乾蝕刻矽。 -------------------------- A-9
圖 A.14 元件製程示意圖:LPCVD二氧化矽。 --------------------- A-9
圖 A.15 元件製程示意圖:內部阻絕層的形成。 ------------------ A-10
圖 A.16 元件製程示意圖:沉積矽鍺薄膜。 ---------------------- A-10
圖 A.17 元件製程示意圖:源汲極區曝光後顯影。 ---------------- A-11圖 A.18 元件製程示意圖:蝕刻矽鍺薄膜。 ---------------------- A-11
圖 A.19 元件製程示意圖:離子佈植形成源╱汲極區。 ----------- A-11

表目錄
頁數
表3-1:bVMOS、bMOS與bSGMOS特性比較表 ----------------------- 40
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[45] Hiromasa Noda, Fumio Murai, and Shin’ichiro Kimura, “Short Channel Characteristics of Si MOSFET With Extremely Shallow Source and Drain Regions Formed by Inversion Layers” IEEE Transactions on Electron Devices, VOL. 41, NO. 1O, OCTOBER 1994.
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