臺灣博碩士論文加值系統

隨著行動電子產品需求的快速成長，非揮發性半導體記憶體也越來越受到重視。在本論文裡，將針對最新型SONOS-type快閃記憶體的抹除機制及性能做深入的探討。此外，一種藉由延長雷射脈衝時間的低溫退火技術也將在本篇中討論，此低溫技術適用於將鐵電電容置於導線之上的鐵電記憶體，以作為系統單晶片之應用。
在新型SONOS-type快閃記憶體的研究中，我們提出並驗證了MANOS元件的抹除機制是一種電子由缺陷跳脫的行為。此外，藉由一種暫態分析的分法，MONOS、 MANOS及BE-SONOS三種元件的抹除機制及電荷儲存能力將可被公平的比較。藉由對抹除機制的了解，一種具創新性的BE-MANOS結構也在本論文中首次提出，此結構具有抑制抹除飽和及加大記憶窗之能力。然而，BE-MANOS之電荷儲存能力卻遠不及BE-SONOS，此問題主要是導因於氧化鋁薄膜無法有效阻絕電荷流失。因此，我們導入一層二氧化矽緩衝層，介於氧化鋁及氮化矽之間，此具二氧化矽緩衝層的BE-MANOS結構不但具有良好的性能，而且改善了電荷流失的問題。另外，在此研究中，我們也釐清了氧化鋁薄膜及二氧化矽緩衝層在電荷阻障層中所扮演的角色。
延長雷射脈衝時間的退火技術將可以提供較多的能量及充分的時間，給予PZT薄膜作為結晶之用，然而，底層的塊材卻依然可以保持在低溫之中。在此研究中，我們針對雷射退火的熱模擬也有所著墨，藉由熱模擬不但可以得知試片中溫度的分佈，也可以了解使用延長脈衝雷射的好處。因此，此新型低溫雷射退火技術，將適用於嵌入式鐵電電容在導線上的鐵電記憶體，以作為系統單晶片之應用。

Non-volatile semiconductor memories have attracted much attention due to the fast growing demand of portable electronic devices. In this thesis, the erase mechanism and the performance of the state of the art SONOS-type flash memories are critically examined, and a low temperature extended-pulse laser annealing for COI FeRAM is also studied.
In the study of innovative SONOS-type flash memories, a de-trapping model for the erase mechanism of MANOS device is proposed and demonstrated. In addition, the erase and retention characteristics for MONOS, MANOS and BE-SONOS devices are fairly compared by using the transient analysis method. Moreover, an innovative BE-MANOS is proposed to overcome the erase saturation and to enlarge the memory window. However, the retention of BE-MANOS is not as good as BE-SONOS owing to the charge leakage through Al2O3 film. By inserting a SiO2 buffer layer between Al2O3 and SiN storage layer, the oxide-buffered BE-MANOS shows good performance and good reliability, and the roles of high-k Al2O3 and SiO2 buffer layer are also clarified in this work.
An extended-pulse laser annealing is used to provide sufficient thermal energy and time into the PZT film to complete the crystallization, while the bulk of materials remains at low temperature. In this work, the thermal simulation is also presented to illustrate the temperature distribution in the specimen and the benefits of the extended pulse. This new low temperature process is suitable for embedded COI FeRAM for SoC applications.

Contents

Abstract (Chinese)……………..……………………………………….......I
Abstract (English)……………..……………………………………….......II
Acknowledgement (Chinese)……………………….……………………III
Contents…………………………………………………………………..IV
List of Tables……………………………………………………………...IX
List of Figures…………………………………………………………….…X

Chapter 1 Introduction……..……………………………………..………1
1.1 Prelude…………………………………………..……………..………………..1
1.2 Motivation……………………………………………………………………….3

Chapter 2 Literature Review……..……………………….…..…..………5
2.1 Semiconductor Memory…………………………………………………………5
2.2 Flash Memory…………………………………………………………………….6
2.2.1 History of Flash Memory……………………….……………………….6
2.2.2 What is Flash Memory?……..………………………………..…………..8
2.2.3 Array Architecture of Flash Memory…………………………………..10
2.2.4 Reliability of NAND Flash Memory…………………………………….12
2.2.5 Scaling Challenges of Floating Gate NAND Flash Memory………..…15
2.2.6 SONOS Flash Memory………………………………………….……..19
2.3 Ferroelectric Random Access Memory (FeRAM)…………………………….23
2.3.1 Ferroelectric Materials…………………………………………………..23
2.3.2 Unit Cell of FeRAM…………………………………..…………….…...24
2.3.3 Capacitor-Over-Interconnect (COI) FeRAM………………………….25
2.4 Summary………………………………………………………………………...25

Chapter 3 Study of MANOS (Metal/Al2O3/SiN/SiO2/Si) Device………..51
3.1 Introduction……………………………………………………………….…..51
3.2 Experimental Description…………………………………………………..….52
3.3 MANOS vs. TANOS…………………………………………………………….53
3.4 Transient Analysis……………………………………………………………....54
3.5 Study of MANOS Erase Mechanism…………………………………..………55
3.6 Processing Effect on MANOS Device………………………………..…..……61
3.7 Summary…………………………………………………………………….…..65

Chapter 4 A Study on the Erase and Retention Mechanisms for MONOS, MANOS, and BE-SONOS Non-Volatile Memory Devices…………….…82
4.1 Introduction…………………………..……………………………………….82
4.2 Experimental Description…………………………………………………..…83
4.3 Comparisons of Erase Speed and Erase Transient Current…………………84
4.4 Erase Mechanisms of MONOS, MANOS and BE-SONOS………………….85
4.5 Erase Saturation Level…………………………………………………………86
4.6 Retention Characteristics………………………………………………..…….87
4.7 Summary………………………………………………………………………...87

Chapter 5 BE-MANOS: A Bandgap Engineered SONOS using Metal Gate and Al2O3 Blocking Layer to Overcome Erase Saturation………..93
5.1 Introduction…………………………..………………………..……………….93
5.2 Experimental Description……………………………………………………...94
5.3 Results and Discussion………………………………………………………….94
5.4 Summary………………………………………………………………………...97

Chapter 6 An Oxide-Buffered BE-MANOS Charge-Trapping Device and the Role of Al2O3…………………………………………………………..105
6.1 Introduction…………………………..………………………..…..………….105
6.2 Experimental Description…………………………………………………….106
6.3 Gate Material Effect of BE-SONOS on Erase Saturation……………….…106
6.4 BE-MANOS with a SiO2 Buffer Layer………………………………………107
6.5 Thickness Dependence of SiO2 Buffer Layer on Erase Characteristics……110
6.6 Thickness Dependence of SiO2 Buffer Layer on Reliability………………..111
6.7 Summary……………………………………………………………………….112

Chapter 7 Extended-pulse Excimer Laser Annealing on Pb(Zr1-xTix)O3 Thin Film on LaNiO3 Electrode………………………..………………..128
7.1 Introduction…………………………………..……..……..………………….128
7.2 Experimental Description…………………………………………………….130
7.3 Thermal Simulation…………………………………………………………...131
7.4 Laser Annealing of the Partially Crystalline PZT Films……………………136
7.5 Laser Annealing of the Amorphous PZT Films……………………………..138
7.6 Summary……………………………………………………………………….139

Chapter 8 Summary…………….……………………..………………….146

Chapter 9 Future Prospects…………………………..…………………..149
9.1 Study of Charge Trapping NAND Flash Memory…………………………..149
9.2 Study of Extended-pulse Laser Annealing for Low Temperature Processes……………………………………………………………………….150

Reference…………………….………………………..…………………...151














List of Tables

Table 2.1 Market share of NAND flash memory by branded revenue………………..31
Table 2.2 Comparisons between solid-state drive (SSD) and hard disk (HDD)……...32
Table 2.3 Performance comparisons between NOR and NAND flash……..………….36
Table 3.1 The programming characteristics of MAOS and MANOS devices………..73
Table 4.1 The detailed film stacks and the gate materials of MONOS, MANOS and BE-SONOS.……………………………………………………………………………….88
Table 5.1 Typical parameters of BE-SONOS, MANOS and BE-MANOS devices in this work.………………………………………………………………………………….98
Table 6.1 Typical device structures used in this work.…………………….………..113
Table 7.1 The thermal properties of all the used materials at 27℃………………….142








List of Figures

Fig. 2.1 Categories of semiconductor memory………………………………………….27
Fig. 2.2 Summary of semiconductor memories………………………………………..27
Fig. 2.3 Revenue partitions of (a) Semiconductor devices and (b) Semiconductor memories in 2006…………………………………………………………………………28
Fig. 2.4 Revenue forecast of semiconductor memories………………………………...28
Fig. 2.5 History of flash memories………………………………………………………29
Fig. 2.6 Applications and main suppliers of NOR flash memory……………………29
Fig. 2.7 Applications and main suppliers of NAND flash memory……………………30
Fig. 2.8 Market share of flash memories………………………………………………..30
Fig. 2.9 Application demand of NAND flash memory………………………………….31
Fig. 2.10 (a) MOS transistor and (b) Flash memory cell………………………………32
Fig. 2.11 Concept of flash memory………………………………………………………33
Fig. 2.12 Operation methods of floating gate flash memory…………………………..33
Fig. 2.13 (a) The equivalent circuit of NOR array flash memory and (b) the cross-sectional view of NOR flash along the bit line direction………………………..34
Fig. 2.14 Operation methods of NOR flash memory…………………………………...34
Fig. 2.15 (a) The equivalent circuit of NAND array flash memory and (b) the cross-sectional view of NAND flash along the bit line direction………………………35
Fig. 2.16 The equivalent circuits and voltages of NAND flash memory during (a) programming, and (b) erasing…………………………………………………………..35
Fig. 2.17 The equivalent circuits and voltages of NAND flash memory during read operation…………………………………………………………………………………36
Fig. 2.18 Scaling roadmap of FG-type NAND flash memory………………………….37
Fig. 2.19 Cycling endurance of flash memory if electrons are trapped inside the tunnel oxide……………………………………………………………………………………….37
Fig. 2.20 Band diagrams of tunnel oxide during data retention with (a) electrons and (b) holes in the floating gate……………………………………………………………38
Fig. 2.21 Schematic model of trap assisted tunneling………………………………….38
Fig. 2.22 (a) Operation voltages of NAND flash memory during read operation, and (b) soft program happens during read operation………………………………………39
Fig. 2.23 The behaviors of tail bits. (a) Number of tail bits after P/E cycles, and (b) Reappearing rate of tail bits……………………………………………………………..39
Fig. 2.24 SEM micrograph of NAND flash memory…………………………………40
Fig. 2.25 Gate coupling ratio as a function of design rule……………………………..40
Fig. 2.26 Schematic illustration of FG-FG interference………………………………41
Fig. 2.27 Reduced floating gate interference due to low-k dielectric material……….41
Fig. 2.28 Number of stored electrons in a NAND flash cell and the tolerable amount of the charge loss in each technology node………………………………………………..42
Fig. 2.29 (a) Scaling trend of DRAM, Flash and MPU/ASIC, and (b) Prediction of the corresponding lithography tool for each technology nodes……………………………42
Fig. 2.30 Schematic cell structure of SONOS flash memory…………………………..43
Fig. 2.31 (a) schematic cell structure of TANOS, and (b) SEM micrograph of TANOS device……………………………………………………………………………………43
Fig. 2.32 Energy band diagram of (a) SONOS and SANOS with poly-Si gate, and (b) SANOS with TaN metal gate at the erase mode………………………………………..44
Fig. 2.33 Data retention characteristics of TANOS devices at bake temp. of 250℃…44
Fig. 2.34 (a) Program and (b) erase characteristics of 63 nm NAND-type TANOS devices……………………………………………………………………………………..45
Fig. 2.35 Endurance of 63 nm NAND-type TANOS devices and floating-gate cells…45
Fig. 2.36 Cell Vth distribution of 64M cells by multi-level cell programming………46
Fig. 2.37 (a) schematic cell structure of BE-SONOS, and (b) the typical process condition of BE-SONOS…………………………………………………………………46
Fig. 2.38 Bandgap engineering concept for the BE-SONOS device…………………..47
Fig. 2.39 (a) Comparison of the –FN erase speed of BE-SONOS (15/20/25/70/90 Å), SONOS (20/70/90 Å) and SONOS (25/70/90 Å). The bias voltages are selected to make these samples to have approximately the same electric field. (b) Comparison of the 150 oC baking retention test for SONOS and BE-SONOS. A wide range of PV state (up to +4 V) and EV states (down to EV= -2V) are tested.…………………………….47
Fig. 2.40 Erase speed comparison for BE-SONOS with various ONO tunneling dielectrics………………………………………………………………………………….48
Fig. 2.41 P/E cycle endurance of the P+-poly gate capacitor…………………………..48
Fig. 2.42 Unit cell of a ABO3 perovskite structure……………………………………..49
Fig. 2.43 Schematic hysteresis loop of a ferroelectric capacitor……………………….49
Fig. 2.44 A unit cell of the destructive read-out (DRO) 1T/1C FeRAM………………50
Fig. 2.45 Cross-sectional diagram of COI FeRAM…………………………………….50
Fig. 3.1 (a) Erase curves and (b) program curves of Pt-gate MANOS, and (c) erase curves of TANOS…………………………………………………………………………67
Fig. 3.2 (a) Erase transient (VFB-time) curves of MANOS with various erase biases, and (b) J-E curves transformed from the VFB-time curves of Fig. 3.2 (a)…………...68
Fig. 3.3 (a) The erase curves of MONOS and MANOS devices. (b) The J-ETUN curves transformed from the erase curves with various erase biases shown in (a) by the transient analysis method. ………………………………………………………………69
Fig. 3.4 (a) Erase curves (VFB-time) of MANOS with different gate materials (Al and Pt). (b) J-E curves of Al-gate MANOS and Pt-gate MANOS………………………….70
Fig. 3.5 The erase curves with different re-fill conditions. The erase voltages are (a) -14V, and (b) –16V, respectively…………………………………………………………71
Fig. 3.6 The dependence of erase temperature on the erase characteristics of MANOS. (a) VFB-time curves with various erase biases and temperatures, and (b) J-E curves transformed from (a).……………………………………………………………………71
Fig. 3.7 The erase characteristics of MANOS erased from (a) PV state (VFB = 4V) and (b) fresh state (VFB = -0.8V), respectively……………………………………………….72
Fig. 3.8 The J-E curves transformed from Fig. 3.7…………………………………….72
Fig. 3.9 The structures used to study the roles of SiN and Al2O3. (a) MAOS device, (b) MNOS device and (c) MANOS device…………………………………………………..73
Fig. 3.10 The erase characteristics of (a) MANOS and (b) MAOS with various erase biases………………………………………………………………………………………74
Fig. 3.11 The J-E curves of MANOS and MAOS transformed from Fig. 3.10……….74
Fig. 3.12 Erase curves of Pt gate MNOS device with various erase biases…………..75
Fig. 3.13 Programming curves of P+ poly gate MNOS device with various programming biases by – FN tunneling………………………………………………..75
Fig. 3.14 TEM cross-sectional views of ANO dielectric with various annealing temperatures for 60 seconds……………………………………………………………..76
Fig. 3.15 (a) Erase curves of the MANOS devices with various post-annealing temperatures for the Al2O3 blocking layer. (b) The J-ETUN plot transformed from the erase curves by transient analysis……………………………………………………….76
Fig. 3.16 Retention characteristics of Pt gate MONOS and Pt gate MANOS………..77
Fig. 3.17 Erase transient current densities of MANOS devices with various Al2O3 deposition methods………………………………………………….……………………77
Fig. 3.18 Retention characteristics of Pt gate MANOS devices at 150 oC……………78
Fig. 3.19 Gate-injection current of the MANOS capacitors with different Al2O3 post-annealing temperature……………………………………………………………..78
Fig. 3.20 Erase curve of MANOS and the corresponding transient electric field in tunnel oxide and Al2O3 during the erasing……………………………………………..79
Fig. 3.21 Retention characteristics of MANOS devices with various annealing temperatures……………………………………………………………………………..79
Fig. 3.22 Retention characteristics of MANOS devices at various baking temperatures……………………………………………………………………………..80
Fig. 3.23 Erase characteristics of MANOS devices with different annealing atmosphere (oxygen and nitrogen) at 950 oC for 60 sec. (a) Erase transient (VFB-time) curves with various erase biases, and (b) J-E curves…………………………..………81
Fig. 3.24 Retention characteristics of MANOS devices with different annealing atmosphere (oxygen and nitrogen) at 950 oC for 60 sec………………………………..81
Fig. 4.1 Schematic structures of (a) MONOS, (b) MANOS, and (c) BE-SONOS devices……………………………………………………………………………………..88
Fig. 4.2 Erase transient (VFB-time) curves of MONOS, MANOS and BE-SONOS with various bias voltages……………………………………………………………………..89
Fig. 4.3 J-E curves of MONOS, MANOS, and BE-SONOS during the erasing……..89
Fig. 4.4 Schematic band diagram to illustrate the erase mechanisms of (a) MONOS, (b) MANOS, and (c) BE-SONOS………………………………………………………..90
Fig. 4.5 Long-term erase characteristics of MONOS, MANOS and BE-SONOS……91
Fig. 4.6 Transient electric fields in tunnel oxide (TUN) and top dielectric (TOX) for MONOS, MANOS and BE-SONOS during the erase………………………………….91
Fig. 4.7 Retention characteristics of MONOS, MANOS and BE-SONOS baked at 150 oC…………………………………………………………………………………………..92
Fig. 5.1 Structures of (a) BE-SONOS, (b) MANOS, and (c) BE-MANOS devices…...98
Fig. 5.2 Erase transient (VFB-time) curves for these 3 devices at VG= -18V…………..99
Fig. 5.3 J-E curves of the 3 devices extracted by the transient analysis.……………...99
Fig. 5.4 Erase transient (VFB-time) curves of BE-MANOS with various O1 thickness at VG= -18V……………………………………………………………………………...100
Fig. 5.5 J-E curves of BE-MANOS with various O1 thickness extracted by the transient analysis………………………………………………………………………..100
Fig. 5.6 Erase transient (VFB-time) curves of BE-MANOS with various O1 and O2 thickness at VG = -18V………………………………………………………………….101
Fig. 5.7 J-E curves of BE-MANOS with various O1 and O2 thickness extracted by the transient analysis………………………………………………………………………..101
Fig. 5.8 Programming characteristics of (a) BE-SONOS and (b) BE-MANOS with various programming bias voltages……………………………………………………102
Fig. 5.9 Erase transient (VFB-time) curves of BE-MANOS, BE-SONOS and MANOS with different gate materials at VG = -20V…………………………………………….103
Fig. 5.10 Transient electric fields in the O1 of ONO tunneling barrier and in the blocking layer for BE-MANOS and BE-SONOS with different gate materials during the erase at VG= -20V…………………………………………………………………..103
Fig. 5.11 Data retention of Pt gate BE-MANOS at 85 oC……………………………..104
Fig. 6.1 TEM micrograph of BE-MANOS with a SiO2 buffer layer…………………113
Fig. 6.2 Erase characteristics of MONOS (with Pt gate), and BE-SONOS with different gate materials. Al (n-type), TiN (mid-gap) and Pt (P-type) gate are compared………………………………………………………………………………...114
Fig. 6.3 Erase characteristics of BE-MANOS with a SiO2 buffer layer (S4) at different erase bias voltages……………………………………………………………………….114
Fig. 6.4 Erase characteristics of BE-SONOS with various top dielectric structures (O3 + Al2O3)…………………………………………………………………………………..115
Fig. 6.5 Erase speed comparison of BE-MANOS with different thickness combinations of O3 and Al2O3 (S4 and S5)……………………………………………116
Fig. 6.6 Erase hole tunneling current density for various BE-SONOS type devices..116
Fig. 6.7 Schematic band diagram to illustrate the gate electron injection in the conduction band of BE-SONOS, BE-MANOS and BE-MANOS with a SiO2 buffer layer………………………………………………………………………………………117
Fig. 6.8 Read disturb characteristics of (a) BE-MANOS with a SiO2 buffer layer (S4), and (b) BE-MANOS (S3)………………………………………………………………118
Fig. 6.9 Read number vs. Vread curves of BE-MANOS with a SiO2 buffer layer (S4) and BE-MANOS (S3)…………………………………………………………………119
Fig. 6.10 Retention of MANOS and various BE-SONOS type devices………………119
Fig. 6.11 P/E cycling endurance test of BE-MANOS with a SiO2 buffer layer (S4)...120
Fig. 6.12 Bake retention of BE-MANOS with a SiO2 buffer layer after different P/E cycles (S4)………………………………………………………………………………..120
Fig. 6.13 Erase characteristics of Pt-gate BE-SONOS and Al-gate BE-MANOS with various thicknesses of SiO2 buffer layers at VG= -15 V……………………………….121
Fig. 6.14 Erase transient current density extracted from Fig. 6.13………………….121
Fig. 6.15 Erase speed comparison of MANOS with and without oxide buffer layer..122
Fig. 6.16 Retention characteristics of BE-MANOS with various thicknesses of oxide buffer layers at 150 oC baking…………………………………………………….……122
Fig. 6.17 Read disturb test of BE-MANOS (13/20/25/50/40/60) with oxide buffer layer……………………………………………………………………………………123
Fig. 6.18 Read disturb of BE-MANOS with a 4 0 Å SiO2 buffer layer, extracted from Fig. 6.17.…………………………………………………………………………………123
Fig. 6.19 Read disturb characteristics of BE-MANOS with different thicknesses of SiO2 buffer layers……………………………………………………………………….124
Fig. 6.20 Cycling endurance of BE-MANOS with different thicknesses of SiO2 buffer layers...…………………………………………………………………………………124
Fig. 6.21 Retention comparison of BE-MANOS with oxide buffer layer, TiN gate BE-SONOS, BE-MANOS without oxide buffer layer, and MANOS without oxide buffer layer……………………………………………………………………………..125
Fig. 6.22 Erase characteristics of BE-MANOS with different Al2O3 thickness……..126
Fig. 6.23 Data retention of BE-MANOS with a SiO2 buffer layer but various Al2O3 thicknesses at 150 oC baking……………………………………………………………126
Fig. 6.24 Band diagrams of (a) SiO2 top dielectric, (b) thin Al2O3 with a SiO2 buffer layer, (c) thick Al2O3 with a SiO2 buffer layer during the erase. (d) Band diagram during data retention…………………………………………………………………...127
Fig. 7.1 Cross-sectional illustration of embedded COI FeRAM……………………140
Fig. 7.2 (a) Schematic illustration of pulse extender, and (b) pulse extender action..140
Fig. 7.3 (a) Schematic illustration of the laser power density for a short pulse and an extended pulse, (b) the temperature transient profiles (temperature vs. time) in PZT films, (c) the temperature distribution in the specimens……………………………..141
Fig. 7.4 SEM top-view micrographs of the partially crystalline PZT films, which are (a) non-laser-annealed, (b) laser annealed by a short-pulse laser system at 45 mJ/cm2 per pulse, (c) laser annealed by an extended-pulse laser system at 150 mJ/cm2 per pulse……………………………………………………………………………………...142
Fig. 7.5 (a) Normalized remanent polarizations of the partially crystalline PZT capacitors, which are laser-annealed by the extended-pulse and the short-pulse laser annealing systems (measured by the PUND method), (b) the hysteresis curve of (I), (c) the hysteresis curve of (II)……………………………………………………………143
Fig. 7.6 TEM micrographs of the partially crystalline PZT films after extended-pulse laser annealing at 150 mJ/cm2 per pulse with (a) 0 shot (non-laser-annealed), (b) 100 shots, (c) 1,000 shots, (d) 10,000 shots………………………………………………….144
Fig. 7.7 (a) The electrical pulses of the PUND method, (b) the relationship between 2Pr and the programming pulse width of the partially crystalline PZT capacitors after being laser-annealed by an extended-pulse laser system at 150 mJ/cm2 per pulse……………………………………………………………………………………145

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