本篇論文提出一個高效能的分數移動預估器之設計應用於H.264/AVC影像編碼。此提出的移動預估器設計架構包含了三個可以平行運算的引擎以達到高生產率。此外我們也提出一套客製化的仲裁機制，應用於我們的三運算引擎之資源共享，且此資源共享的方法可以減少使用計算sum of absolute transformed difference 50%硬體合成面積。我們使用TSMC 130nm COMS製程技術合成此移動預估器之設計，於166萬赫茲工作頻率下，合成出約311700個邏輯閘。此設計執行在154萬赫茲工作頻率，可以支援1080pHD的即時影像壓縮。比較於其他相關的論文提出的設計架構，我們提出的分數移動預估器之設計架構可以在較低的工作頻率下，支援相同的影像壓縮且擁有相對較佳的影像品質與較佳的影像壓縮率。

Abstract 4
Content 5
List of Figures 6
List of Tables 8
Chapter 1 Introduction 9
1.1 Fractional Motion Search Policy 12
1.2 Fractional Motion Estimation Cost Function 12
1.3 Luma Sample Interpolation 13
1.4 Contribution and Thesis Organization 14
Chapter 2 Preliminary and Previous Work 16
2.1 FME Task Preliminary 16
2.2 Previous Work 20
2.3 Design Goal and Considerations 23
Chapter 3 Proposed Architecture 26
3.1 Three-Engine FME Architecture 27
3.1.1 The First Stage of Engine 1 and Engine 2 27
3.1.2 The Second Stage of Engine 1 and Engine 2 32
3.1.3 FME Architecture of Engine 3 35
3.2 Input Data Scheduler 37
3.2.1 Reference Pixel Scheduling and Bandwidth-Hardware Trade-off 37
3.2.2 Reference Pixel Memory Architecture 39
Chapter 4 Proposed Resource Sharing Method 41
4.1 SATD Generator Usage Analysis 41
4.2 SATD Generator Allocation 42
4.3 Arbitration Scheme 44
Chapter 5 Implementation Results 47
Chapter 6 Conclusion and Future Work 51
Bibliography 52

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