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研究生:劉哲宇
研究生(外文):Che-Yu Liu
論文名稱:考慮單元轉換時間之去耦合電容配置方法以用於減少供電干擾
論文名稱(外文):Transition-Aware Decoupling-Capacitor Allocation in Power Noise Reduction
指導教授:黃婷婷黃婷婷引用關係
指導教授(外文):TingTing Hwang
學位類別:碩士
校院名稱:國立清華大學
系所名稱:資訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:96
語文別:英文
論文頁數:34
中文關鍵詞:去耦合電容Decap供電干擾Power Noise
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隨著製程的不斷進步,現在晶圓的密度變得越來越高,加上運行速度也不斷地在上升,使得有越來越多項目會在同時發生轉換,因此造成晶圓上電力供應被干擾的情況變得越來越嚴重。電力供應的不穩,會引發許多嚴重的問題,其中最重要的就是會使整個晶圓的效能降低,更甚者,連功能都會發生錯誤。所以穩定的電力供應在現在的設計上是必須的。

一般來說,最常被用來解決供電干擾的方法是在晶圓上配置一些去耦合電容;去耦合電容的作用如同一個電子銀行,在平時它會儲存著電荷,當單元做轉換有需要時,它便會將其電荷釋放出來供單元做轉換使用,因此能夠有效降低供電干擾。我們發現影響供電干擾的因素,除了單元的位置之外,單元的轉換時間也是相當重要的。

在這篇論文裡,我們提出了兩個解決供電干擾的方法:首先,我們會在佈局之前,先去考慮單元的轉換時間以及單元的位置,預測哪些單元可能會發生很嚴重的供電干擾,在這些供電干擾嚴重的單元旁邊,我們先綁住一些去耦合電容,藉由這些被綁在單元旁邊的去耦合電容,我們可以在佈局之前先解決部分的供電干擾的問題;接下來,在佈局之後,我們提出另一個搬動單元的方法進一步解決供電干擾。在這個方法裡,我們會藉由改變原本單元擺放的位置,去減少原本供電干擾很嚴重的地方的干擾來源,使得整個晶圓上的電力需求變得更平均,因此也就能確實解決供電干擾的問題。
1 Introduction 1

2 Previous Work 6
2.1 Decap Allocation at Floorplan Level 6
2.2 Decap Allocation After Placement 7
2.3 Decap Allocation Before Placement 8

3 Modeling and Analysis of Power Supply Network 11

4 Design Flow 13

5 Algorithms 15
5.1 Decap Padding 15
5.2 CellMoving 20

6 Experimental Result 26

7 Conclusions 32
[1] Chao-Yang Yeh and Malgorzata Marek-Sadowska, ”Timing-aware Power Noise Reduction in Layout,” International Conference on Computer-Aided Design (ICCAD), pp. 627-634, Nov., 2005.

[2] Sanjay Pant and David Blaauw, ”Timing-aware Decoupling Capacitance Allocation in Power Distribution Networks,” Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 757-762, Jan., 2007.

[3] S. Pant, D. Blaauw, V. Zolotov, S. Sundareswaran, and R. Panda, ”Vectorless Analysis of Supply Noise Induced Delay Variation,” International Conference on Computer-Aided Design (ICCAD), pp. 184-191 , Nov., 2003.

[4] H. Su, S. S. Sapatnekar, and S. R. Nassif, ”Optimal Decoupling Capacitor Sizing and Placement for Standard-cell Layout Designs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.22, issue 4, pp. 428-436, Apr., 2003.

[5] Y. Zhong, and Martin D. F. Wong, ”Fast Algorithms for IR Drop Analysis in Large Power Grid,” International Conference on Computer-Aided Design (ICCAD), pp. 351-357 , Nov., 2005.

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[7] Ang-Chih Hsieh, Tzu-Teng Lin, Tsuang-Wei Chang, and TingTing Hwang, ”A functionality-directed clustering technique for low-power MTCMOS designXcomputation of simultaneously discharging current,”ACM Transactions on Design Automation of Electronic Systems (TODAES).

[8] H. Kriplani, F. N. Najm, and I. N. Hajj, ”Pattern Independent Maximum Current Estimation in Power and Ground Buses of CMOS VLSI Circuits: Algorithms, Signal Correlations, and Their Resolution,”IEEE Transactions
on Computer-Aided Design of Integrated Circuits and Systems, pp.998-1012, 1995.

[9] L. T. Pillage, R. A. Rohrer, and C. Visweswariah, ”Electronic Circuit and System Simulaton Methods,” McGraw-Hill, 1995.

[10] Bo Hu and Malgorzata Marek-Sadowska, ”Wire Length Prediction Based Clustering and Its Application in Placement,” Design Automatin Conference (DAC), pp. 800-805, 2003.

[11] M. Pan, N. Viswanathan, and C. Chu, ”An Efficient and Effective Detailed Placement algorithm,” International Conference on Computer-Aided Design (ICCAD), pp. 48-55, 2005.

[12] S. Zhao, K. Roy, and C. K. Kon, ”Decoupling Capacitance Allocation and Its Application to Power-Supply Noise-Aware Floorplanning”, IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems (Special Issue on Physical Design), 21(1), january 2002, pp. 81-92.

[13] R. Dutta and M. M. Sadowska, ”Automatic sizing of power/ground networks in VLSI,” in Proc. Design Automation Conf., June 1989.

[14] K.-H. Erhard, F. M. Johannes, and R. Dachauer, ”Topology optimization techniques for power/ground networks in VLSI,” in Proc. Eur. Design Automation Conf., pp. 362-367, Mar. 1992.

[15] M. Ang, R. Salem, and A. Taylor, ”An on-chip voltage regulator using switched decoupling capacitors,” in Proc. Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 438-439, Feb. 2000.

[16] B. Obermeier, F. M. Johannes, ”Temperature-aware global placement,”Proceeding of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair 2004, January 27-30, 2004, Yokohama, Japan.
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