跳到主要內容

臺灣博碩士論文加值系統

(44.221.70.232) 您好!臺灣時間:2024/05/29 03:35
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

: 
twitterline
研究生:林俊吉
研究生(外文):Chun-Chi Lin
論文名稱:一種一般性的邏輯結構重整技術:非冗餘的移除及添加
論文名稱(外文):A Universal Logic Restructuring Technique: IRredundancy Removal and Addition
指導教授:王俊堯王俊堯引用關係
指導教授(外文):Chun-Yao Wang
學位類別:碩士
校院名稱:國立清華大學
系所名稱:資訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:96
語文別:英文
論文頁數:27
中文關鍵詞:邏輯結構重整冗餘
相關次數:
  • 被引用被引用:0
  • 點閱點閱:172
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
電路的冗餘添加和移除以及基於自動測試圖樣產生/診斷的設計重新繞線都是用於邏輯設計電路中的合成和優化的重組技術。這兩種技巧可以移除一條存在目標電路線,然後連接另一條本來不在電路上的電路線使得電路的功能是沒有受到改變的。不過在這兩種方法中,由於一些限制,並非每一條電路線都可以成功地找到另一條電路線去取代它。此外,在基於自動測試圖樣產生/診斷的設計重新繞線方法中,需要去驗證重組之後的電路功能有沒有改變。因此,本文提出了一種一般性的邏輯結構重整技術,稱為非冗餘的移除及添加,它可以去移除任何想要移除的目標電路線。非冗餘的移除及添加這個技術建構出相對應的修正電路去修正由於移除目標電路線所造成的錯誤。在本文中,非冗餘的移除及添加技術被用在兩個應用,分別是搜尋替代線路及電路面積優化。實驗結果顯現,使用非冗餘的移除及添加方法在搜尋替代線路上比起之前的方法更有效。在電路面積優化上,跟SIS比較,結果非常令人激勵。
書頁名 - i
論文口試委員審定書 - ii
授權書 - iii
中文摘要 - iv
Abstract - v
Acknowledgements -vi
Contents - vii
List of Tables - ix
List of Figures - x
1. Introduction - 1
2. Notations and background - 4
3. Irredundancy removal and addition - 6
4. Single alternative wire identication using the IRRA approach - 12
4.1 SMA classification - 14
4.2 SMA substitution - 16
5. Area optimization using the IRRA approach - 18
6. Experimental Results - 20
7. Conclusions - 25
References - 25
[1] C.-W. Jim Chang, M.-F. Hsiao, and M. Marek-Sadowska, \A New Reason-
ing Scheme for Ecient Redundancy Addition and Removal," IEEE Trans.
Computer-Aided Design, vol. 22, pp. 945-952, July 2003.
[2] S.-C. Chang, K.-T. Cheng, N.-S Woo, and M. Marek-Sadowska, \Postlayout
Logic Restructuring Using Alternative Wires," IEEE Trans. Computer-Aided
Design, vol. 16, pp. 587-596, June 1997.
[3] K. T. Cheng and L. A. Entrena \Multi-level Logic Optimization by Redundancy
Addition and Removal," in Proc. Europ. Conf. Design Automation, pp. 373-377,
1993.
[4] S.-C. Chang, M. Marek-Sadowska, and K.-T. Cheng, \Perturb and Simplify:
Multi-level Boolean Network Optimizer," IEEE Trans. Computer-Aided Design,
vol. 15, pp. 1494-1504, Dec. 1996.
[5] S.-C. Chang, L. P. P. P. Van Ginneken, and M. Marek-Sadowska, \Fast Boolean
Optimization by Rewiring," in Proc. Int. Conf. Computer-Aided Design, pp.
262-269, 1996.
[6] Y.-C Chen and C.-Y Wang, \An Improved Approach for Alternative Wires
Identication," in Proc. Int. Conf. Computer Design, pp. 711-716, 2005.
[7] L. A. Entrena and K.-T. Cheng, \Combinational and Sequential Logic Op-
timization by Redundancy Addition and Removal," IEEE Trans. Computer-
Aided Design, vol. 14, pp. 909-916, July 1995.
[8] T. Kirkland and M. R. Mercer, \A Topological Search Algorithm for ATPG,"
in Proc. Design Automation Conf., pp. 502-508, 1987.
[9] W. Kunz and D. K. Pradhan, \Recursive Learning: An Attractive Alternative
to the Decision Tree for Test Generation in Digital Circuits", in Proc. Int. Test
Conf., pp. 816-825, 1992.
[10] E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H.
Savoj, P. R. Stephan, R. K. Brayton, and A. Sangiovanni-Vincentelli, \SIS: A
System for Sequential Circuit Synthesis," Technical Report UCB/ERL M92/41,
Electronics Research Lab, Univ. of California, Berkeley, CA 94720, May 1992.
[11] A. Veneris and M. S. Abadir, \Design Rewiring Using ATPG", IEEE Trans.
Computer-Aided Design, vol. 21, pp.1469-1479, Dec. 2002.
[12] A. Veneris, J. B. Liu, M. Amiri and M. S. Abadir, \Incremental Diagnosis and
Debugging of Multiple Faults and Errors", in Proc. Design, Automation and
Test in Europe, pp. 716-721, 2002.
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top