臺灣博碩士論文加值系統

金屬/鐵電層/絕緣層/半導體電晶體作為揮發性記憶體元件具有許多優點。在本論文中，我們對金屬/絕緣層/半導體電容器、金屬/鐵電層/絕緣層/半導體電容器與電晶體施以不同的表面處理並量測其電性。在本實驗中，我們使用二種表面處理方式，在沉積絕緣層薄膜之前施以過氧化氫(H2O2)前處理(pre-treatment)和沉積絕緣層之後施以氯化氫(HCl)後處理(post-treatment)。在經過表面處理過後的鋁/氧化鋯/矽電容器，介面態從5.62x1013/cm2降低至4.0x1012/cm2，氧化鋯薄膜(7nm)加上過渡層的整體複合介電常數從5.54增加至7.3。經過表面處理之後，分別以X射線光電子能譜 (X-ray photoelectron spectroscopy)以及二次離子質譜儀(secondary ion mass spectrometry) 觀察到鋯-氧鍵束縳能的增加以及鋯原子擴散的減少。
我們進一步探討經過表面處理之後鋁/鋯鈦酸鉛(PZT)/氧化鋯/矽電容器的電性。經過表面處理之後鋁/鋯鈦酸鉛/氧化鋯/矽電容器的漏電流在5伏特時從10-1 A/cm2 降至5.4x10-6 A/cm2，記憶保存時間從13小時延長至17.1天。記憶保存時間得以延長的原因是經過表面處理後，閘極漏電流大幅降低了104。經過表面處理的鐵電電晶體(FeFET)在3000秒之後依然能夠維持一個大約1.1伏特的臨界電壓窗口。臨界電壓斜率也從311 mV/dec改進到91 mV/dec。鐵電電晶體在經過脈波寬度為0.1 ms ，+8和-8 伏特的極化過程之後，洩極電流的開關比為103。鐵電電晶體效能改進的原因是閘極漏電流的降低以及氧化鋯/矽介面態的改善。
鋁/鋯鈦酸鉛/氧化釔/矽電容器在經過表面處理後，在5伏特時的漏電流從10-3 A/cm2降至5.4x10-6 A/cm2。未經表面處理的試片在正偏壓增加下有較大的平帶電壓偏移(1.5伏特)，而經過表面處理的試片在相同的情形下，平帶電壓偏移只有0.8伏特。這顯示未經表面處理的試片在正偏壓增加時會有較多的載子注入。經過表面處理的鋁/鋯鈦酸鉛/氧化釔/矽鐵電電晶體在5000秒之後依然維持一個大約1.5伏特臨界電壓的窗口。鐵電電晶體在經過脈波寬度為100 ns ，+8和-8 伏特的極化過程之後，洩極電流的開關比大約為105。這些效能改進的原因可以歸之於經過表面處理後，閘極漏電流的降低以及載子注入的減少。

In this thesis, the electrical properties of Al/Pb(ZrTi)O3/insulator/Si capacitors and field effect transistors with various surface treatments were studied. The wafers were given a H2O2 pre-treatment before insulator layer deposition and a HCl post-treatment after deposition. For the case of Al/ZrO2/Si capacitors with surface treatments, the interface state density was reduced from 5.62x1013/cm2 to 4.0x1012/cm2 and the composite dielectric constant of ZrO2 film (about 7 nm) plus interfacial layer was increased from 5.54 to 7.3. The binding energy of the Zr-O bond was increased and the Zr out-diffusion was decreased based on X-ray photoelectron spectroscopy (XPS) and secondary ion mass spectrometry (SIMS) results, respectively.
The leakage current density of Al/PZT/ZrO2/Si capacitors with both treatments was improved from 10-1 A/cm2 to 5.4x10-6 A/cm2 at 5 V and the retention time of Al/PZT/ZrO2/Si capacitors was improved from 13.3 hours to 17.1 days. The longer retention time of Al/PZT/ZrO2/Si capacitor with surface treatments was attributed to the reduced gate leakage current. The FeFETs with both treatments maintain a threshold voltage window of about 1.1 V after an elapsed time of 3000 sec. The subthreshold slope was improved from 311 mV/dec to 91 mV/dec. The drain current on/off ratio of FeFETs with both treatments was about 103. The improvements are most likely due to the reduction of the leakage current and the interface states at the ZrO2/Si interface.
Al/PZT/Y2O3/Si FeFETs with both treatments were also fabricated. The leakage current density at 5 V is reduced from 10-3 A/cm2 to 10-6 A/cm2. Samples with no treatment show a much larger flat band voltage shift ΔVFB of 1.5 V compared to that of 0.8 V with both treatments. It means more electrons are injected into the insulator layer with no treatment as the positive bias is increased. The best FeFETs maintain a threshold voltage window of about 1.5 V after an elapsed time of 5000 sec. The drain current on/off ratio of FeFETs with both treatments after applying writing pulses of +8 V and -8 V with a duration of 100 ns was about 105. The improvements are most likely due to the reduction of the gate leakage current and the charge injection effect.

Contents

Chapter 1 Introduction
1.1 Non-Volatile Memories------------------------------------------------------------------001
1.2 Ferroelectricity - FRAM and FeFETs -------------------------------------------------003
1.3 Development of FeFET------------------------------------------------------------------004
1.4 Outline of this thesis ---------------------------------------------------------------------005

Chapter 2 Failure Mechanisms
2.1 Depolarization Field----------------------------------------------------------------------007
2.2 Leakage Current and Charge Injection------------------------------------------------ 011

Chapter 3 Fabrication Process of Memory Devices
3.1 Fabrication process of Al/ZrO2/Si capacitors-----------------------------------------013
3.2 Fabrication process of MFIS capacitors and FeFETs
3.2.1 MFIS capacitors--------------------------------------------------------------------013
3.2.2 FeFETs ------------------------------------------------------------------------------014

Chapter 4 Electrical Properties of Al/ZrO2/Si Capacitors with Surface Treatments
4.1 Literature Survey of Surface Treatment on High-k Insulator -----------------------016
4.2 Physical Analysis--------------------------------------------------------------------------017
4.3 Electrical Analysis-------------------------------------------------------------------------018

Chapter 5 Electrical Properties of Al/PZT/ZrO2/Si Capacitors and Transistors with Surface Treatments
5.1 Material Consideration-------------------------------------------------------------------021
5.2 C-V curve orientation-Memory window ----------------------------------------------022
5.3 C-V curve orientation-Charge Injection -----------------------------------------------022
5.4 C-V Characteristic of Al/PZT/ZrO2/Si Capacitors -----------------------------------023
5.5 J-V Characteristic of Al/PZT/ZrO2/Si Capacitors ------------------------------------024
5.6 Retention Properties of Al/PZT/ZrO2/Si Capacitors ---------------------------------024
5.7 Electrical Properties of Al/PZT/ZrO2/Si Transistors ---------------------------------025

Chapter 6 Electrical Properties of Al/PZT/Y2O3/Si Capacitors and Transistors with Surface Treatments
6.1 Introduction -------------------------------------------------------------------------------028
6.2 C-V Characteristic of Al/PZT/Y2O3/Si Capacitors with no treatment-------------029
6.3 Conduction Mechanism of Al/PZT/Y2O3/Si Capacitors with no treatment-------030
6.4 Electrical Properties of Al/PZT/ Y2O3/Si Transistors with no treatment ----------033
6.5 C-V Characteristic of Al/PZT/Y2O3/Si Capacitors with both treatments----------035
6.6 Electrical Properties of Al/PZT/ Y2O3/Si Capacitors and Transistors with both treatments----------------------------------------------------------------------------------036

Chapter 7 Conclusion and Future Work
7.1 Conclusion----------------------------------------------------------------------------------038
7.2 Future work---------------------------------------------------------------------------------040

Reference------------------------------------------------------------------------------------- 041
Figures and Tables------------------------------------------------------------------------047
Vita ---------------------------------------------------------------------------------------------112
Publish list -----------------------------------------------------------------------------------113

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J. W. Lee, Y. S. Jeong, H.D. Jeong, T.H. Min, J.H. Cho, Y.C. Jeong, Y. J. Kim, “Fabrication and characterization of a new EEPROM cell with spacer select transistor,” EDL Vol.26, Issue 8, pp. 569 - 571 (2005).
C.Y.S.Cho, M. J. Chen, C. F. Chen, D. T. Fan, T. Y. Liu, “A novel self-aligned highly reliable sidewall split-gate flash memory,” TED, Vol.53, Issue 3, pp. 466 - 473 (2006).
A. L.Lacaita, “Physics and Performance of Phase Change Memories,” IEEE Simulation of Semiconductor Processes and Devices (SISPAD) International Conference on, pp. 267-268(2005).
S. Y. Lee and K. Kim, “Current Development Status and Future Challenges of Ferroelectric Random Access Memory Technologies” Jpn. J. Appl. Phy., Vol.45, No.4B, pp.3189-3193(2006).
H. Kohlstedt, Y. Mustafa, A. Gerber, A. Petraru, M. Fitsilis, R. Meyer, U. BÃÃttger, R. Waser, “Current status and challenges of ferroelectric memory devices,” Micro. Engineering, Vol. 80, pp. 296-304(2005).
P. Zurcher, R.E. Jones, P.Y. Chu, D.J. Taylor, B.E. White, S. Zafar,; B. Jiang; Y. J. Tom Lii, S.J. Gillespie, “Ferroelectric nonvolatile memory technology: applications and integration challenges,” IEEE Trans. Components, Packaging, and Manufacturing Technology, Vol.20, No. 2, pp. 175-181(1997).
J. M. Koo, “Fabrication of 3D trench PZT capacitors for 256Mbit FRAM device application,” IEDM (2005).
Y. K. Hong et al., “130 nm-technology, 0.25 μm2, 1T1C FRAM Cell for SoC (System-on-a-Chip)-friendly Applications,” VLSI, pp. 230-231 (2007).
K. Kim, S. Y. Lee, “Memory technology in the future,” Microeletronic Engineering, Vol. 84, pp. 1976-1981 (2007).
T. Hirai, Y. Fujisaki, “Preparation of SrBi2Ta2O9 Film at Low Temperatures and Fabrication of a Metal/Ferroelectric/Insulator/Semiconductor Field Effect Transistor Using Al/SrBi2Ta2O9/CeO2/Si(100) Structures,” Jpn. J. Appl. Phy., Vol. 36, pp.5908-5911(1997).
E. Tokumosu and H. Sakai, “Data Retention and Readout Degradation Properties of Pt/Sr0.7Sm0.07Bi2.2Ta2O9/HfO2/Si Structure Ferroelectric-Gate Field Effect Transistors” Jpn. J. Appl. Phy., Vol. 46, pp. 261-266(2007).
S. M. Yoon, H. Ishiwara, “Memory operations of 1T2C-type ferroelectric memory cell with excellent data retention characteristics,“ TED, Vol. 48, pp.2002-2208, (2001).
H. Isjiwara, “Current status and prospects of FET-type ferroelectric memories,” FED Journal, Vol. 11, pp. 27-40(2000).
M. Fitsilis, Y. Mustafa, and R. Waser, “Scaling the Ferroelectric Field Effect Transistor” Integ. Ferro., Vol. 70, pp. 29-44(2005).
Y. C. Shin, J.D. Choi, C. S. Kang, C. H. Lee, K. T. Park, J. S. Lee, J. Sel, V. Kim, B. Choi, J. Sim, D. Kim, H. J. Cho and K. Kim, “A Novel NAND-type MONOS Memory using 63nm Process Technology for Multi-Gigabit Flash EEPROMs,” IEDM Tech. Dig., pp. 327-330, 2005.
H. Ishiwara, “Current status and prospects of FET-type ferroelectric memories,” FED Journal, Vol. 11, pp.27-40, 2000.
D. Takashima and I. Kunishima, “High-Density Chain Ferroelectric Radom Access Memory (Chain FRAM),” IEEE J. Solid-State Circuits, Vol. 33, pp. 787-792, 1998.
Y. K. Hong, D. J. Jung, S. K. Kang, H. S. Kim, J. Y. Jung, H. K. Koh, J. H. Park, D. Y. Choi, S. E. Kim, W. S. Ann, Y. M. Kang, H. H. Kim, J.-H. Kim, W. U. Jung, E. S. Lee, S. Y. Lee, H. S. Jeong, and K. Kim, “130 nm-technology, 0.25μm2, 1T1C FRAM Cell for SoC (System-on-a-Chip)-friendly Applications,” VLSI Tech. Dig., pp. 230-231, 2007.
O. Hidaka, T.Ozaki, H.Kanaya, Y.Kumura, Y.Shimojo, S.Shuto, Y.Yamada, K.Yahashi, K.Yamakawa, S.Yamazaki, D.Takashima, T.Miyakawa, S.Shiratake, S.Ohtsuki, I.Kunishima and A.Nitayama, “High Density and High Reliability Chain FeRAM with Damage-robust MOCVD-PZT Capacitor with SrRuO3/IrO2 Top Electrode for 64Mb and Beyond,” VLSI Tech. Dig., pp. 126-127, 2006.
Y. Kato, Y. Kaneko, H. Tanaka, K. Kaibara, S. Koyama, K. Isogai, T. Yamada, and Y. Shimada, “Overview and Future Challenge of Ferroelectric Random Access Memory Technologies,” Jap. J. Appl. Phys., Vol. 46, pp. 2157-2163, 2007.
I. M. Ross, U.S. Patent No. 2791760, 1957.
J. L. Moll and Y. Tarui, “ A New Solid State Memory Resistor,” IEEE Trans. Electron Devices Vol. ED-10, pp. 338-339, 1963.
S. Y. Wu, “A New Ferroelectric Memory Device, Metal-Ferroelectric-Semiconductdr Traktor,” IEEE Trans. Electron Devices Vol. ED-21, pp. 499-504, 1974.
K. Aizawa, B. E. Park, Y. Kawashima, K. Takahashi, and H. Ishiwara, “Impact of HfO2 buffer layers on data retention characteristics of ferroelectric-gate field-effect transistors,” Appl. Phys. Lett., Vol. 85, pp. 3199-3201, 2004.
M. Takahashi and S. Sakai, “Self-Aligned-Gate Metal/Ferroelectric/Insulator/Semiconductor Field-Effect Transistors with Long Memory Retention,” Jap. J. Appl. Phys., Vol. 44, pp. L800-L802, 2005.
S. Kim, J. Koo, S. Shin, and Y. Park, “Improvement of retention loss in Pb(Zr, Ti)O3 capacitors using Ir/SrRuO3 top electrode,” Appl. Phys. Lett., Vol. 87, Page No. 212910, 2005.
I. P. Brtra, P. Wurfel and B. D. Silverman, “Depolarization field and Stability Considerations in Thin Ferroelectric Films,” J. Vac. Sci. Technol., Vol. 10, pp.687-692, 1973.
Y. Watanabe and D. Sawamura, “Thermodynamic Stability of the Spontaneous Polarization and the Space Charge Layer in Ferroelectric/Semiconductor Heterostructues,” Jpn. J. Appl. Phys., Vol. 36, pp. 6162-6166, 1997.
T. Li, S. T. Hsu, B. D. Ulrich, L. Stecker, E. R. Evans and J. J. Lee, “One Transistor Ferroelectric Memory With Pt/Pb5Ge3O11/Ir/Poly-Si/SiO2/Si Gate Stack”, IEEE Electron Device Letters, vol. 23, pp.339-341, 2002.
C. T. Black, C. Farrell and T. Licata, “Suppression of ferroelectric polarization by an adjustable depolarization field,” Appl. Phys. Lett., Vol. 71, pp. 2041-2043, 1997.
T. P. Ma, J.P. Han, “Why is Nonvolatile Ferroelectric Memory Field-Effect Transistor Still Elusive?” IEEE Electron Device Letters, vol. 23, pp.386-388, 2002.
M. Okuyama and M. Noda, “Improvement of Memory Retention in Metal-Ferroelectric-Insulator-Semiconductor (MFIS) Structures,” Topics Appl. Phys., Vol. 98, pp. 219-239, 2005.
S. Bühlmann, E. Colla and P. Muralt, “Polarization reversal due to charge injection in ferroelectric films,” Phys. Rev. B, Vol. 72, Page No. 214120,2005.
S. K. Lee, Y. T. Kim and S. Kim, “Effects of coercive voltage and charge injection on memory windows of metal-ferroelectric-semiconductor and metal-ferroelectric-insulator-semiconductor gate structures,” J. Appl. Phys., vol. 91, pp. 9303-9307, 2002.
P. C. Juan, Y. P. Hu, F. C. Chiu and J. Y. M. Lee, “The charge trapping effect of metal-ferroelectric (PbZr0.53Ti0.47O3)-insulator (HfO2)-silicon capacitors,” J. Appl. Phys., vol.98, p. 044103, 2005.
S. Zafar, A. Callegari, E. Gusev, and M. Fischetti, “Charge trapping related threshold voltage instabilities in high permittivity gate dielectric stacks,” J. Appl. Phys., 93, no. 11, pp. 9298–9303, Jun. 2003.
J. Zhu, T. P. Ma, S. Zafar, and T. Tamagawa, “Charge trapping in ultrathin hafnium oxide,” IEEE Electron Device Lett., 23, no. 10, pp. 597–599, Oct. 2002.
E. P. Gusev and C. P. D’Emic, “Charge detrapping in HfO2 high-k gate stacks,” Appl. Phys. Lett., 83, no. 25, pp. 5223–5225, Dec. 2003.
A. Kerber, E. Carter, L. Pantisano, M. Rosmeulen, R. Degraeve, T. Kauerauf, G. Groeseneken, H. E. Maes, and U. Schwalke, “Characterization of VT instability in SiO2/HfO2 gate dielectrics,” in Proc. 41st Int. Reliab. Phys. Symp., Dallas, TX, 2003, p. 41.
M. S. Akbar, N. Moumen, J. Barnett, B. H. Lee and Jack C. Lee, “Improvement in bias instabilities of Hf-silicate by dilute hydrochloric acid (500:1) post-deposition rinsing and its effect after high-pressure H2 anneal,” Appl. Phys. Lett., 87, p. 252903, 2005.
X. Wang, J. Peterson, P. Majhi, M. I. Gardner, and Dim-Lee Kwong, “Threshold Voltage (Vth) Instability in HfO2 High-k Gate Stacks With TiN Metal Gate: Comparison Between NH3 and O3 Interface Treatments,” IEEE Electron Device Lett., 25, no. 11, pp. 719-721, Nov. 2004.
M. S. Akbar, N. Moumen, J. Barnett, J. Sim and Jack C. Lee, “Effect of NH3 surface nitridation temperature on mobility of ultrathin atomic layer deposited HfO2,” Appl. Phys. Lett., 86, pp. 032906-1-032906-3, 2005.
S. J. Doh, H. S. Jug, Y. S. Kim, H. J. Lim, J. P. Kim, J. H. Lee, J. H. Lee, N. I. Lee, H. K. Kan , K. P. Suh, S. G. Park, S. B. Kang, G. H. Choi, Y. S. Chung, H. S. BaiK, H. S. Chaug, M. H. Cho, D. W. Moon, H. B. Park, M. Cho , C. S. Hwang, “Improvement of NBTI and Electrical Characteristics by Ozone Pre-treatment and PBTL issues in BtAIO(N) High-k Gate Dielectrics,” in Proc. IEEE IEDM, 2003, pp. 943-946.
C. Driemeiera and L. Miotti, I. J. R. Baumvol, C. Radtke, E. P. Gusev, M. J. Kim and R. M. Wallace, “Interaction of HfO2 /SiO2 /Si structures with deuterium gas,” Appl. Phys. Lett., 88, p. 041918, 2006.
W. T. Lu, C. H. Chiein, W. T. Lan, T. C. Lee, P. Lehnen, and T. Y. Huang, “Improved Reliability of HfO2/SiON Gate Stack by Fluorine Incorporation,” IEEE Electron Device Lett., 27, no. 4, pp. 240-242, April. 2006.
K. I. Seo, R. Sreenivasan, P. C. McIntyre, and K. C. Saraswat, “Improvement in High-k (HfO2/SiO2) Reliability by Incorporation of Fluorine,” IEEE Electron Device Lett., 27, no.10, pp. 821-823, Oct. 2006.
L. Wang, K. Xue, J. B. Xu, A. P. Huang and Paul K. Chu, “Control of interfacial silicate between HfO2 and Si by high concentration ozone,” Appl. Phys. Lett., vol. 88, Article No. 072903, 2006.
C. J. Huang, M. P. Houng, Y. H. Wang, N. F. Wang and J. R. Chen, “Improved Formation of Silicon Dioxide Films in Liquid Phase Deposition,” J. Vac. Sci. Technol. A, vol. 16, no. 4, Jul/Aug, 1998.
M. Balog, M. Schieber, M. Michman and S. Patai, “Basic developments in optical coatings,” Thin Solid Films, 41, pp.247-259, 1977.
W. C. Shih, K. Y. Kang and Joseph Y. M. Lee, “The Improvement of Retention Time of Metal-Ferroelectric (PbZr0.53Ti0.47O3)-Insulator (ZrO2)-Semiconductor Transistors and Capacitors by Leakage Current Reduction Using Surface Treatment”, Appl. Phys. Lett., Vol. 91, Article No. 192906 (2007).
C. N. Berlund, "Surface States at Steam-Grown Silicon-. Silicon Dioxide Interfaces”, IEEE trans. Electron Dev., ED-13, pp. 701-705, 1966.
S. M. Sze, Physics of Semiconductor Devices, 2nd, Wiley, New Work, 1981.
F. C. Chiu, Z. H. Lin, C. W. Chang, C. C. Wang, K. F. Chuang, C. Y. Huang, J. Y. M. Lee, and H. L. Hwang, “Electron conduction mechanism and band diagram of sputter-deposited Al/ZrO2/Si structure,” J. Appl. Phys., Vol. 97, p. 034506, 2005.S. M. Sze, Physics of Semiconductor Devices, 2nd, Wiley, New Work, 1981.
M. Ross, U.S. Patent No. 2,791,760, 1957.
J. F. Scott, Ferroelectric Memories, Springer-Verlag, Berlin, 2001, Chap. 12, pp. 175-178.
Wouters, Dirk J.; Willems, Geert J. Maes, E. Herman, “Electrical Conductivity in Ferroelectric Thin Films,” Microelectron Eng. Vol., 29, pp. 249-256(1995).
P. C. Fazan, “High-Dielectric constant thin films for dynamic random access memory (DRAM),” Integ. Ferroelec., Vol., 4, p. 247 (1994).
Y. Xu, “Ferroelectric Materials and Their Applications.” Elsevier Science,
Amsterdam, 1999.
M. Takashi, H. Yoshimori, H. Watanabe, Carlos A. Paz de Araujo, “Characteristics of Bismuth Layered SrBi2Ta2O9 Thin-Film Capacitors and Comparison with Pb(Zr, Ti)O3” Jpn. J. Appl. Phys. Vol., 34, p. 5233-5239(1995).
H. Watanabe, IEICE Trans. Electron. E76-C, 1564 (1993).
R. Ramesh, Ed., “Thin Film Ferroelectric Materials and Devices.” Kluwer Academic, Boston, 1997.
M. E. Lines and A. M. Glass, “Principles and Applications of Ferroelectrics and Related Materials.” Clarendon, Oxford, (1977).
Z. G. Zhang, J. S. Liu, Y. N. Wang, J. S. Zhu, J. L. Liu, D. Su, and H. M. Shen, “Structure and voltage dependence of ferroelectric properties of SrBi2Ta2O9 thin films” J. Appl. Phys. Vol., 85, pp. 1746-1749 (1999).
R.W. Schwartz et al, “Preparation and characterization of chemically derived (Pb,La)TiO3 thin films” IEEE Trans. Ultrasonics, Ferroelectrics and Frequency Control 38, pp. 677-683(1991).
S. K. Dey and J. J. Lee, “Cubic paraelectric (nonferroelectric) perovskite PLT thin films with high permittivity for ULSI DRAMs and decoupling capacitors” IEEE Trans. Electron Devices, Vol. 39, pp. 1607-1613(1992).
Parashar, A R Raju, C. N. R Rao, P. Victor and S B Krupanidhi, “Electrical properties of ferroelectric YMnO3 films deposited on n-type Si(111) substrates,” J. Phys. D: Appl. Phys. Vol., 36, pp.2134-2140(2003).
D. ITO, N. Fujimura and T. Ito, “Initial Stage of Film Growth of Pulsed Laser Deposited YMnO3” Jpn. J. Appl. Phy., Vol. 39, pp. 5525-5527(2000).
T. Li, Maxim Lebedev, “Powder Preparation in Aerosol Deposition Method for Lead Zirconate Titanate Thick Films,” Jpn. J. Appl. Phys., Vol. 41, pp. 6890-6984(2002).
S. Ohara, K. Aizawa, H. Ishiwara, “Ferroelectric Properties of Pt/Pb5Ge3O11/Pt and Pt/Pb5Ge3O11/HfO2/Si Structures” Jpn. J. Appl. Phys., Vol. 44, No. 9A, pp. 6644–6647(2005).
M. Houssa, High-κ Gate Dielectrics, Institute of Physics Publishing, UK, Appendix, p. 597, 2004
C. H. Ahn, J.-M. Triscone, N. Archibald, M. Decroux, R. H. Hammomd, T. H. Geballe, F. Fischer, and M. R. Beasley, “Ferroelectric Field Effect in Epitaxial Thin Film Oxide SrCuO2/Pb(Zr0.52Ti0.48)O3 Heterostructures”, Science, Vol. 269, 373 (1995).
M. Houssa, High-κ Gate Dielectrics, Institute of Physics Publishing, UK, Appendix, p. 597, 2004.
H. Iwai, S. Ohmi, S. Akama, C. Ohshima, A. Kikuchi, I. Kashiwagi, J. Taguchi, H. Yamamoto, J. Tonotani, Y. Kim, I. Ueda, A. Kuriyama, Y. Yoshihara, “Advanced gate dielectric materials for sub-100 nm CMOS”, IEDM Tech. Dig., pp. 625-628, 2002.
K. Suzuki, D. Fu, K. Nishizawa, T. Miki, and K. Kato, “Preparation of (Y,Yb)MnO3/Y2O3/Si (MFIS) Structure by Chemical Solution Deposition Method”, Jpn. J. Appl. Phys., Vol. 42, pp. 6007-6010, 2003.
D. Ito, N. Fujimura, T. Yoshimura, and T. Ito, “Influence of Schottky and Poole–Frenkel emission on the retention property of YMnO3-based metal/ferroelectric/insulator/semiconductor capacitors”, J. Appl. Phys., Vol. 94, no.6, pp. 4036-4041, 2003.
T. Kanashima and M. Okuyama, “Analyses of High Frequency Capacitance–Voltage Characteristics of Metal-Ferroelectrics-Insulator-Silicon Structure”, Jpn. J. Appl. Phys., Vol. 38, pp. 2044-2048, 1999.
B. E. Park, S. Shouriki, E. Tokumitsu, and H. Ishiwara, “Fabrication of PbZrxTi1-xO3 Films on Si Structures Using Y2O3 Buffer Layers “, Jpn. J. Appl. Phys., Vol. 37, pp. 5145-5149, 1998.
C. Y. Chang, T. P. C. Juan, and J. Y. M. Lee, “Fabrication and characterization of metal-ferroelectric (PbZr0.53Ti0.47O3)-insulator (Dy2O3)-semiconductor capacitors for nonvolatile memory applications”, Appl. Phys. Lett., Vol. 88, Article No. 072917, pp. 1-3, 2006.
W. J. Zhu, T. P. Ma, T. Tamagawa, J. Kim, and Y. Di, “Current transport in metal/hafnium oxide/silicon structure”, IEEE Trans. Electron Device Letters, Vol. 23, pp. 97-99, 2002.
J. F. Scott, “Questions of Effective Masses in Ferroelectric FETs”, Integrated Ferroelectrics, Vol. 42, pp. 1-11, 2002.
H. P. R. Frederikse ans G. A. Candela, “Magnetic Susceptibility of Insulating and Semiconducting Strontium Titanate“, Phy. Rev., Vol. 147, p. 583, 1966.
C. N. Berglund and W. S. Baer, “Electron Transport in Single-Domain, Ferroelectric Barium Titanate”, Phys. Rev., Vol. 157, p. 358, 1967.
A. S. Barker, “Optical Properties and Electronic Structure of Metal and Alloys”, ed. F. Abeles (North-Holland, Amsterdam), p. 452, 1996.
J. G. Simmon, “Conduction in thin dielectric films”, J. Phys. D: Appl. Phys., Vol. 4, pp. 613-657, 1971.
J. P. McKelvey, Solid State and Semiconductor Physics, New York, 1971.
J. Yu, Z. Hong, W. Zhou, G. Cao, J. Xie, and X. Li, “Formation and characteristics of Pb(Zr,Ti)O3 field-effect transistor with a SiO2 buffer layer”, Appl. Phys. Lett., Vol. 70, no. 4, pp. 490-492, 1997.
A. Chin, M.Y. Yang, C. L. Sun, and S. Y. Chen, “Stack gate PZT/Al2O3 one transistor ferroelectric memory”, IEEE Electron Device Letters, Vol. 22, pp. 336-338, 2001.
B. Park, K. Takahashi and H. Ishiwara B. Park, “Fabrication and electrical properties of Pt/ (Bi,La)4Ti3O12/HfO2/Si structures”, J. Korea Phys. Soc., Vol. 46, pp. 346-349, 2005.
B. E. Park, H. Ishiwara, H, “Fabrication of MFIS diodes using BLT (Bi,La)4Ti3O12/ and LaAlO3 buffer layers”, Proceedings of the 13th IEEE International Symposium on Applications of Ferroelectrics (ISAF), Yokohama, Japan, pp. 163-166, 2002.
C. Chien, D. Wang, M. Yang, P. Lehnen, C. Leu, S. Chuang, T. Huang, C. Y. Chang, “High-performance Pt/SrBi2Ta2O9/HfO2/Si structure for nondestructive readout memory”, IEEE Electron Device Letters, Vol. 24, pp. 553-555, 2003.