臺灣博碩士論文加值系統

The purpose of this study is to develop a high-density and high-performance phase change memory (PCM). To evaluate the programming characteristics of PCM device, a comprehensive numerical model and suitable measurement systems were developed and built. The typical mushroom-type PCM devices were fabricated to act as the platform of characteristic exploration. The programming characteristics, endurance, data retention, and multilevel programming capability of PCM devices were thoroughly investigated to acquire the critical factors in device characteristics and the failure mechanisms. The experimental results indicate that the optimization in programming pulse width and heater material is important for avoiding the incomplete SET programming which is a major mechanism responsible for endurance failure. A new double-confined PCM structure was proposed to reduce the programming current. In addition to the current constriction of the traditional confined structure, the double-confined device adds a thermal insulation layer under the active region to provide the thermal confinement. Thus the thermal efficiency is greatly improved and both the programming current and power consumption are reduced. The experimental results demonstrate that the double-confined device may be the promising candidate for high-density PCM. To further boot the memory capacity, a novel PCM multilevel storage scheme with wide programming margins was proposed and evaluated by an established comprehensive parameterized PCM HSPICE model. The simulation and experimental results demonstrate that the novel multilevel storage scheme can be realized and the serial PCM structure is preferable for high-density applications due to its lower programming current and smaller cell area. In conclusion, this study gives a rather thorough exploration of PCM device characteristics which is beneficial to improve the device performances. The results demonstrate that the developed PCM devices can meet the promised device performances in terms of low programming current (< 0.3 mA), fast programming speed (< 50 ns), good endurance (> 1E6 cycles), and long data retention (> 10 years at 85 ℃). Therefore, this PCM technology has great potential to become the next-generation mainstream nonvolatile memory.

本論文之研究動機為開發一具有高密度與高性能之相變化記憶體。為了評估相變化記憶體元件的操作特性，本研究發展一套功能強大的數值模型用於進行元件的熱電模擬工作，並建立適用的測試系統以作為元件的特性量測之用。本研究採用典型的mushroom-type相變化記憶體元件結構來作為元件特性的研究平台，元件的操作特性、耐久度、資料保存能力、以及多階操作等特性在本研究中被完整地探討，藉此可獲知影響元件特性的關鍵因素與元件失效的主要機制。由研究結果顯示不完全SET操作為造成耐久度失效的主要機制，而藉由操作脈波與heater材料的最佳化則可改善此不完全SET操作可能造成的問題。為了有效地降低相變化記憶體元件的操作電流，本研究乃提出一種新型的double-confined device的元件結構，此結構不但具有傳統confined device電流侷限的特性，藉由加入一熱絕緣層於操作區之下亦可同時提供熱侷限的效果。因此，採用double-confined device 可大大地提升元件的熱效率，因而可有效地降低元件的操作電流與功率損耗。由實驗結果也證實了double-confined device有極大的潛力可被應用於高密度的相變化記憶體。除了降低操作電流之外，實現相變化記憶體的多階操作亦為增加記憶體密度的有效作法。有鑑於此，本研究亦提出了一新型且具有較大操作區間的多階操作方法，並利用一套已建立的PCM HSPICE電路模型來模擬此多階操作的概念。由電路模擬與初步實驗的結果證實了此新型多階操作的可行性，且結果顯示串聯式的PCM元件結構因具有較低的操作電流與較小的元件面積，因而較適合應用於高密度的相變化記憶體。綜合言之，本研究提供了有關相變化記憶體元件特性的完整探討，所得的結果將有助於改善相變化記憶體的元件特性。本研究所開發的相變化記憶體元件可達成具競爭性的元件特性，包括：操作電流可低於0.3 mA、操作速度可快於50 ns、耐久度可高於1E6 cycles、以及資料保存能力在85 ℃的溫度之下可長於十年。因此，此相變化記憶體技術能夠達成高密度與高性能的目標，具有極大的潛力可成為下個世代的主流非揮發性記憶體技術。

ABSTRACT
ACKNOWLEDGEMENTS TABLE OF CONTENTS
LIST OF TABLES
LIST OF FIGURES

CHAPTER 1 INTRODUCTION
1.1 History of Phase Change Memory
1.2 Principles of Phase Change Memory 1.2.1 Chalcogenide Alloys
1.2.2 Storage Mechanisms (Reading and Writing)
1.2.3 Storage Element and Array Architecture
1.3 Purpose of Study
1.3.1 High-densiy PCM
1.3.2 Improvement of PCM Device Performances

CHAPTER 2 DEVELOPMENT STATUS OF PHASE CHANGE MEMORY TECHNOLOGY
2.1 Materials for Phase Change Memory
2.2 Device Structures
2.3 Fundamental Characteristics
2.3.1 Electrical Characteristics - I-V Curve and R-I Curve
2.3.2 Reliability Characteristics - Endurance and Data Retention
2.4 Array Architecture
2.5 PCM Scalability

CHAPTER 3 NUMERICAL MODEL AND MEASUREMENT SETUP
3.1 Numerical Model
3.1.1 Simulation Procedure
3.1.2 Descriptions of Numerical Model
3.2 Measurement Setup
3.2.1 Illustration of Measurement Setup
3.2.2 Measurement Items
3.2.2.1 Basic Device Characteristics
3.2.2.2 Programming Speed
3.2.2.3 Reliability Capabilities

CHAPTER 4 INVESTIGATION OF PCM DEVICE CHARACTERISTICS
4.1 Mushroom-type Structure
4.1.1 Device Structure and Process Integration
4.1.2 Device Characteristics
4.1.2.1 I-V and R-I Curves
4.1.2.2 Programming Speed
4.1.2.3 Reliability and Uniformity
4.1.2.4 Multilevel Programming and Direct Overwrite
4.2 Impact of Incomplete SET Programming
4.2.1 Thermal Simulation of SET Programming
4.2.2 Pulse Width Dependent Device Characteristics
4.2.3 Physical Model of Performance Degradation
4.3 Summary

CHAPTER 5 OPTIMIZATION OF PCM DEVICE STRUCTURE
5.1 Double-confined Structure
5.2 Process Integration
5.3 Thermal Simulation
5.4 Electrical Characterization
5.5 Summary

CHAPTER 6 NOVEL MULTILEVEL STORAGE SCHEME
6.1 PCM HSPICE Behavioral Model
6.1.1 Device Characteristics
6.1.2 Descriptions of PCM HSPICE Model
6.1.3 Simulation Results of PCM HSPICE Model
6.2 Novel Scheme of PCM Multilevel Storage
6.3 Demonstration of Novel Multilevel Storage by HSPICE Model
6.4 Experimental Results
6.5 Summary

CHAPTER 7 CONCLUSIONS

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