臺灣博碩士論文加值系統

快閃記憶體誕生的30年來，全世界隨著「摩爾定律」之下，不斷的追求高密度、操作更快速的記憶體， 使得記憶體在大約3年一個世代的推衍下不斷的微縮，當IC技術往奈米級推進，快閃記憶體所衍生出的問題也越來越多。因此在過去的數十年來針對快閃記憶體微縮後所遇到的問題的研究的文獻甚多，也有致力於其它的新型記憶體架構的研究，都是為了因應未來記憶體容量提升的需求。一般認為，在元件微縮後所導致的可靠度及操作干擾的問題，將會造成快閃記憶體縮小的極限。
因此，本論文中主要有兩項工作，第一、提出以缺陷輔助穿隧模型(trap assisted tunneling model) 及Poole Frenkel Effect模型為基礎，探討其在ETOX及SONOS兩種架構下資料主要的流失機制。
另一項工作則是建構出在ETOX及SONOS兩種架構下，預測資料保存能力的模型，加入一些機率的參數，利用MATLAB程式來幫助元件的模擬及預測，並提供不同記憶體之結構與操作參數改變對資料保存能力的影響。並利用模擬結果來搭配文獻中所得之量測結果以證明此模擬程式的準確性及利用模擬來討論其中元件結構變化對記憶體可靠度及縮小化極限的影響。

Flash Memories are used extensively various portable electronic products. The Moore’s law predicts that flash memory cells scale down one generation in two to three years. When IC technology scales to nanometer feature size, flash memories will face many challenges. To further increase memory density, many researchers propose new cell structure, innovative operations and array architectures on cell. However, issues on cell reliability and disturbance are generally believes to put the ultimate limit on cell size..
In this work, two major subjects are investigated. First, the basic model on the data loss in the ETOX and SONOS cells is proposed by combing the trap assisted tunneling and Poole Frenkel leakage currents.
In addition, a data retention characteristic in ETOX and SONOS cells are predicted by the model. Using a MATLAB program, the data retention characteristics for devices with various structures are estimated. This simulated result shows fairly good agreements with data reported in the literature.

內文目錄

Abstract………………………………………………………………………….. i
摘要……………………………………………………………………………... ii
誌謝……………………………………………………………………………... iii
內文目錄………………………………………………………………………... iv
圖片目錄………………………………………………………………………... v
第一章 論文大綱……………………………………………………………... 1
第二章 文獻回顧……………………………………………………………...
2.1 記憶體概論…………………………………………………………..
2.2 快閃記憶體發展…………………………………………………….. 2
2
2
第三章 基本物理……………………………………….……………………..
3.1 快閃記憶體寫入、抹除機制………………………………………..
3.1.1 FN 注入………………………………………………………
3.1.2 通道熱載子注入……………………………………………...
3.1.3 FN 抹除………………………………………………………
3.2 NAND陣列和NOR陣列…………………………………………….
3.2.1 NOR 陣列…………………………………………………….
3.2.2 NAND 陣列…………………………………………………..
3.3 電容耦合效應……………………………………………………….. 12
12
12
12
13
13
13
13
15
第四章 模擬環境介紹………………………………………………………...
4.1 模擬軟體簡介………………………………………………………..
4.2 使用的物理模型……………………………………………………..
4.3 模擬方法…………………………………………………………….. 24
24
24
29
第五章 模擬結果與討論…...…………………………………………………
5.1 懸浮極快閃記憶體模擬……………………………………………..
5.2 SONOS、BE-SONOS快閃記憶體模擬………………………………
5.2.1提升O3層材料的介電係數……………………………………
5.2.2減低O1層材料的介電係數……………………………………
5.2.3減低N1層材料的能隙………………………………………… 33
33
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35
35
35
第六章 結論……………...…………………………………………………… 51
參考文獻………………………………………………………………………... 52

參考文獻
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[7] Moon Kyung Kim, SooDoo Chae, Chung Woo Kim, Jooyeon Kim, ” The Effects of ONO thickness on Memory Characteristics in Nano-scale Charge Trapping Devices” 2007 IEEE
[8] Masashi WADA, Shouichi MIMURA, Hiroyuki NIHIRA, ‘’LIMITING FACTORS FOR PROGRAMMING EPROM OF REDUCED DIMENSIONS’’ 1980 IEEE
[9] R.Bez, E.Camerlenghi, D.Cantarelli, L.Ravazzi ”A NOVEL METHOD FOR THE EXPERIMENTAL DETERMINATION OF THE COUPLING RATIOS IN SUBMICRON AND FLASH EEPROM CELLS’’ 1990 IEEE
[10] TIM THURGATE, NELSON CHAN “An Impact Lonization Model for Two-Dimensional Device Simulation” 1985 IEEE
[11] Shoji Shukuri, Natsuo Ajika, Masaaki Mihara, Kazuo Kobayashi, ‘’A 60nm NOR Flash Memory Cell Technology Utilizing Back Bias Assisted Band-to-Band Tunneling Induced Hot-Electron Injection(B4-Flash),’’2006 IEEE
[12] Mohammad Gh, “ Flash Memory Disturbances: Modeling and Test “ Mohammad and Kewal K. Saluja Department of Electrical and Computer Engineering University of Wisconsin, 2001 IEEE
[13] Ming-Hung Chang , “Effect of Device Structure on SONOS Operation Characteristics” Jul,2003.
[14] Intel Corporation , “Intel Strata Flash Memory Technology , Application Note”, Dec 1998.
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