臺灣博碩士論文加值系統

Single Instruction Multiple Data (SIMD) is powerful in multimedia processing. Usually, for a conventional 32-bit machine, if one data unit is 8-bit in width, one SIMD instruction can operate on four units at a time and thus reach data parallelism to four. These data units are often be regarded as subwords in SIMD processing. However, performance of SIMD is restricted by ill subword permutation in register file. Therefore, we propose a new architecture of register file named Vector Register (VR) architecture. With Vector Register, subwords can be well permuted in register file without bringing heavy traffic between memory and register file. We have designed three benchmarks, matrix transposition, deblocking filter, and discrete cosine transform (DCT) based on H.264/AVC, and set up a deliberating simulation flow on Starfish DSP (digital signal processor) simulator. The simulation results shows that, in average, we can improve cycle count, instruction count of these benchmarks to 30.865%, 30.606%, respectively.

在多媒體處理的領域中，由於資料的特性，單一指令操作於多重資料( Single Instruction Multiple Data, SIMD )的運算處理技術是有效及廣泛被使用的。通常，對於一台32-bit的機器來說，假如一個運算資料單位是8-bit的話，一條SIMD的指令可以同時操作於4個資料單位，因此也能將運算的平行度提升到4。這些運算資料單元在SIMD運算處理技術中，時常被稱之為子字符( subword )。然而，SIMD運算的效能常常受限於這些subwords在暫存器( register )之間的排列狀況。因此，為了解決subwords的排列問題，我們提出了一種新的暫存器架構，稱之為向量暫存器架構( Vector Register Architecture )。藉由向量暫存器架構，我們可以更自由地在暫存器間，排列、重組這些subwords，而不需要在暫存器跟記憶體之間，製造大量的資料流量。為了模擬與驗證向量暫存器的效能，我們基於新一代的影像壓縮技術─H.264/AVC，設計了三組標準測試程式( benchmark )，這些程式分別是矩陣轉置( matrix transposition)，去方塊效應濾波器( deblocking filter)，離散餘弦轉換 ( discrete cosine transform)。我們並設計了一套清楚的模擬流程去進行向量暫存器架構的模擬。透過這套流程，我們的模擬結果顯示：向量暫存器架構能有效地降低指令所消耗的週期數( cycle count )，以及所需要的指令數( instruction count )。平均而言，透過向量暫存器架構，我們能分別改善cycle count達到30.865%，instruction count達到30.606%。

Contents
1 Introduction 1
1.1 Research Motivation 1
1.2 Organization of This Thesis 2
2 Starfish DSP Architecture 5
2.1 Introduction 5
2.2 Architecture of Starfish DSP 6
2.2.1 Register File Architecture 6
2.2.2 Pipeline Architecture 7
2.2.3 Instruction Set Architecture 9
2.3 Software Toolkit of Starfish DSP 11
2.3.1 Toolchain 11
2.3.2 Simulator 12
2.3.3 Debuger 13
3 H.264/AVC Video Coding 15
3.1 Introduction 15
3.1.1 Terminologies in H.264/AVC 16
3.1.2 H.264/AVC Encoder 17
3.1.3 H.264/AVC Decoder 20
3.2 Critical Functions in H.264/AVC 20
3.2.1 Discrete Cosine Transform (DCT) 21
3.2.2 Deblocking Filter 24
4 Vector Register Architecture 31
4.1 Introduction 31
4.2 Previous Studies and Works 32
4.3 Principle of Vector Register 33
4.4 Hardware Architecture of Vector Register 34
4.4.1 Register File 34
4.4.2 Status Flag 34
4.5 ISA of Vector Register 34
4.6 Issues Regarding to Vector Register 36
4.6.1 Register Pressure 36
4.6.2 Pipeline Data Hazard Detection and Register Bypassing 37
5 Simulation 43
5.1 Introduction 43
5.1.1 Assumptions and Terminologies 44
5.2 An Overview of Simulation Flow 44
5.3 Modification of Starfish DSP Simulator 44
5.3.1 Principle of Starfish DSP Simulator 44
5.3.2 Implementations of VR instructions 47
5.4 Composing Vector Register Benchmarks 51
5.4.1 Matrix Transposition 51
5.4.2 Deblocking Filter 52
5.4.3 DCT 55
5.5 Code Generation 59
5.6 Simulation Results 61
5.6.1 Matrix Transposition 61
5.6.2 Deblocking Filter 63
5.6.3 DCT 64
5.6.4 Summary 66
6 Conclusion 69

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