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研究生:葉宗浩
研究生(外文):Zong-Hao Ye
論文名稱:電荷陷阱式快閃記憶體元件中堆疊矽化鍺於穿隧氧化層與高介電儲存層之電荷分佈模擬研究
論文名稱(外文):Simulation of SiGe Stacked in Tunneling Layer and Charge Distribution of High-K Charge Trapping Layer in Charge-Trap Flash Device
指導教授:張廖貴術
指導教授(外文):Kuei-Shu Chang-Liao
學位類別:碩士
校院名稱:國立清華大學
系所名稱:工程與系統科學系
學門:工程學門
學類:核子工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:96
語文別:中文
論文頁數:112
中文關鍵詞:快閃記憶體模擬
相關次數:
  • 被引用被引用:0
  • 點閱點閱:235
  • 評分評分:
  • 下載下載:14
  • 收藏至我的研究室書目清單書目收藏:0
本論文分為兩個重點,第一個是以矽化鍺堆疊在電荷-缺陷型式
快閃記憶體之穿隧氧化層,研究這樣的結構對於元件工作特性所造成
的一些影響,在這個部分我們分為幾個部份作為探討主題,首先探討
的是堆疊矽化鍺濃度對於元件效能的影響,接著是堆疊材料不同對於
工作效能的影響,分別就三種不同的半導體材料做研究,分別是矽、
矽化鍺以及砷化鎵。
另外,由於矽化鍺堆疊在電荷-缺陷型式快閃記憶體之穿隧氧化
層中勢必造成穿隧氧化層一分為二,也就是說載子必須經過兩次穿隧
才能到達儲存層,所以堆疊位置造成氧化層分配對於穿隧效果的影響
是我們下一個研究的主題。隨著時代演進,元件微縮是不可避免的,
所以我們也研究短通道時我們的元件工作效能是否會受到嚴重的影
響。
第二個重點我們將介紹以高介電材料堆疊作為電荷-陷阱型式儲
存之快閃記憶體的儲存層,在這部分我們將研究儲存層單層與雙層堆
疊結構在CHEI寫入時的一些電特性,並且就儲存層中電荷分佈做一些
簡單的探討。
摘要............................................. I
誌謝............................................ II
目錄............................................ IV
圖目錄.......................................... IX
表目錄......................................... XIX
第一章 序論...................................... 1
1.1 前言.............................................. 1
1.2 快閃記憶體面臨的問題[1] ........................... 2
1.4 文獻回顧......................................... 5
1.4.1 雙位元快閃記憶體 (2-Bit Flash) .............. 6
1.4.2 P 型通道電荷陷阱式快閃記憶體快閃記憶體...... 6
1.4.3 矽化鍺通道記憶體............................ 7
1.4.4 矽化鍺源/汲極異質介面電晶體................. 9
第二章 以電荷陷阱式快閃記憶體元件的基礎理論與基本
模擬之介紹............................................ 20
2.1 以電荷陷阱式快閃記憶體元件操作方法.............. 20
2.1.1 通道熱電子注入寫入......................... 20
2.1.2 通道熱載子注入的模型....................... 21
V
2.1.3 FN 穿隧寫入................................ 24
2.1.4 FN 穿隧抹除................................ 24
2.1.5 帶對帶穿隧引發熱載子寫入(BBHE) ........... 25
2.2 電荷陷阱式快閃記憶體記憶體元件可靠度特性........ 26
2.2.1 耐力....................................... 26
2.2.2 干擾....................................... 28
2.2.3 電荷保持................................... 29
2.3 模擬軟體介紹.................................... 30
第三章 電荷陷阱式儲存之快閃記憶體使用SiGe、Si 與GaAs
堆疊於穿隧氧化層之研究............................... 43
3.1 研究動機......................................... 43
3.2 不同濃度之矽化鍺堆疊於電荷陷阱式快閃記憶體的穿隧氧化
層.................................................. 44
3.2.1 N 通道電荷陷阱式快閃記憶體的CHEI 與FN 寫入特性
................................................. 45
3.2.2 N 通道電荷陷阱式快閃記憶體的抹除特性....... 47
3.2.3 P 通道電荷陷阱式快閃記憶體的BBHE 寫入特性.. 47
3.2.4 P 通道電荷陷阱式快閃記憶體抹除特性......... 48
3.2.5 N 通道電荷陷阱式快閃記憶體電荷保存力與P 通道電
VI
荷陷阱式快閃記憶體汲極干擾....................... 49
3.2.6 堆疊不同矽化鍺濃度於電荷陷阱式快閃記憶體穿隧氧
化層的結論....................................... 50
3.3 堆疊不同材料之應用............................... 50
3.3.1 N 通道電荷陷阱式快閃記憶體的CHEI 與FN 寫入特性
................................................. 50
3.3.2 N 通道電荷陷阱式快閃記憶體的抹除操作....... 51
3.3.3 BBHE 寫入操作.............................. 52
3.3.4 P-通道電荷陷阱式快閃記憶體抹除操作......... 52
3.3.5 N 通道電荷陷阱式快閃記憶體電荷保存力與P 電荷陷
阱式快閃記憶體汲極干擾........................... 52
3.3.6 堆疊不同矽化鍺濃度於電荷陷阱式快閃記憶體結論53
3.4 結論............................................. 54
第四章 電荷陷阱式快閃記憶體堆疊不同位置矽化鍺於穿
隧氧化層與短通道的研究............................... 65
4.1 研究背景與動機................................... 65
4.2 電荷陷阱式快閃記憶體不同位置的SiGe 堆疊於穿隧氧化層
.................................................... 66
4.2.1 N 通道電荷陷阱式快閃記憶體的CHEI 寫入特性.. 67
VII
4.2.2 N 通道電荷陷阱式快閃記憶體的抹除特性....... 67
4.2.3 P 通道電荷陷阱式快閃記憶體的BBHE 寫入特性.. 68
4.2.4 P 通道電荷陷阱式快閃記憶體抹除操作......... 69
4.2.5 N 通道電荷陷阱式快閃記憶體電荷保存力與P 通道電
荷陷阱式快閃記憶體汲極干擾....................... 70
4.2.6 堆疊矽化鍺於電荷陷阱式快閃記憶體穿隧氧化層的不
同位置對於工作效能的影響之結論................... 70
4.3 短通道效應....................................... 71
4.3.1 N 通道電荷陷阱式快閃記憶體的CHEI 寫入特性.. 71
4.3.2 N 通道電荷陷阱式快閃記憶體的抹除特性....... 71
4.2.3 P 通道電荷陷阱式快閃記憶體的BBHE 寫入特性.. 72
4.2.4 P 通道電荷陷阱式快閃記憶體抹除特性......... 73
4.2.5 N-Channel 電荷陷阱式快閃記憶體電荷保存現象與
P-Channel 電荷陷阱式快閃記憶體汲極干擾........... 73
4.2.6 堆疊矽化鍺於不同通道長度的電荷陷阱式快閃記憶體
的穿隧氧化層對於工作效能的影響之結論............. 74
4.3 結論............................................. 74
第五章 堆疊高介電材料於電荷陷阱式快閃記憶體元件電荷
儲存層的研究.......................................... 87
VIII
5.1 研究動機......................................... 87
5.2 單層高介電係數材料於電荷陷阱式快閃記憶體之電荷儲存層
.................................................... 88
5.2.1 CHEI 寫入特性.............................. 89
5.2.2 電荷隨時間在儲存層儲存的順序............... 89
5.2.3 通道FN 抹除操作............................ 90
5.2.4 單層高介電係數材料於電荷陷阱式快閃記憶體儲存層
工作性能之結論................................... 91
5.3 堆疊雙層高介電係數材料於電荷儲存層............... 91
5.3.1 堆疊雙層高介電係數於電荷陷阱快閃記憶體的CHEI 寫
入特性........................................... 91
5.3.2 堆疊雙層高介電係數於電荷陷阱式快閃記憶體的FN
抹除特性......................................... 93
5.3.3 電荷隨時間在儲存層儲存的順序............... 93
5.3.4 堆疊雙層高介電係數材料於電荷陷阱式快閃記憶體儲
存層工作性能之結論結論........................... 94
5.4 結論............................................. 95
參考資料.............................................. 109
[1] Min She, “Semiconductor Flash Memory Scaling", 2003
[2] Jing Hao Chen, et al., “NonVolatile Flash Memory Device Using Ge Nanocrystals Embedded in HfAlO High-K Tunneling and Control Oxide:Device Fabrication and Electrical Performance",IEEE Transactions on
Electron Devices, Vol.51, No.11,pp.1-29, 2004
[3] Min She, et al., "Impact of crystal size and tunnel dielectric on semiconductor nanocrystal memory performance", IEEE Transactions on Electron Devices, Vol.50, No.9,pp.1934-1940, 2003.
[4] Dong-Won Kim, et al., “Memory characterization of SiGe quantum dot flash memorieswith HfO2 and SiO2 tunneling dielectrics",IEEE Transactions on Electron Devices, Vol.50, No.9,pp.1-7, 2003.
[5] Marvin H. White, et al.,"On the go with SONOS", IEEE Circuit & Device, 2000.
[6] Marvin H. White, et al., “A low voltage SONOS nonvolatile semiconductor memory technology", IEEE Transactions on Components,Packaging, and Manufacturing Technology, Vol.20, No.2, 1997.
[7] Jiankang Bu, et al., “Retention reliability enhanced SONOS NVSM with scaled programming voltage", IEEE Aerospace Conference paper, Vol.5,P5-2383 5-2390, 2001
[8] W. J. Tsai, et al., “Data retention behavior of a SONOS type two-bit storage flash memory cell", IEEE International Electron Devices Meeting,32.6.1-32.6.4, 2001
[9] K. Tamer San, et al., “Effects of erase source bias on Flash EPROM device reliability", IEEE Transactions on Electron Devices , Vol.42,No.1, 1995
[10] 薛富元, “由模擬來探討Floating Gate Memory及電荷陷阱式快閃記憶體 元件微小化之極限", 國立清華大學電子工程研究所, P6, 2004
[11] Jan Van Houdt, et al., “High-k materials for nonvolatile memory applications," International Reliability Physics Symposium,234-239, 2005.
[12] T. Sugizaki, et al., “Novel multi-bit SONOS type flash memory using a high-k charge trapping layer", IEEE Symposium on VLSI Technology Digest of Technical Paper,pp.27-28, 2003.
[13] Chih-Chieh Yeh, et al., “A Novel PHINES Flash Memory Cell with Low Power Program/Erase, Small Pitch, Two-Bits-Per-Cell for Data Storage
110 Applications" IEEE Transactions on Electron Devices, Vol. 52, pp.541-546, 2005
[14] B. Eitan, et al., “NROM: A novel localized trapping, 2-bit nonvolatile memory cell," IEEE Electron Device Letters, No.6, pp.543-545, 2000.
[15] T. Ohnakado, et al.,“Device characteristics of 0.35 μm p-channel DINOR flash memory using band-to-band tunneling-induced hot electron (BBHE) programming," IEEE Transactions on Electron Devices, No.12,pp.1866-1871, 1999.
[16] Hang-Ting Lue, et al.,“A Novel P-Channel Nitride-Trapping Nonvolatile Memory Device with Excellent Reliability Properties,"IEEE Electron Device Letters, VOL. 26, No.8,pp.583-585, 2005.
[17] D. L. Kencke, et al., “Enhanced Secondary Electron Injection in Novel SiGe Flash Memory Devices," IEEE International Electron Device Meeting, pp. 105-108, 2000.
[18] L. M. Weltzer et al.,“Enhanced CHISEL Programming in Flash Memory Devices with SiGe Buried Layer," Non-Volatile Memory Technology Symposium, pp.31-33, 2004
[19] Chi-Chao Wang, et al.,"Enhanced Band-to-Band-Tunneling-Induced Hot-Electron Injection in p-Channel Flash by Band-gap Offset
Modification," IEEE Electron Device Letters, VOL. 27, No.
9,pp.749-751, 2006
[20] S. A. Hareland, et al., “New structural approach for reducing punchthrough current in deep submicrometer MOSFETs and extending MOSFET scaling," IEEE Electronic Letters, Vol. 29, No. 21, pp.
1894-1896, 1993
[21] S. A. Hareland, et al.,“Analysis of a Heterojunction MOSFET Structure for Deep-Submicron Scaling," Proc. of the 21st International Symposium on Compound Semiconductors, pp. 18-22,1994.
[22] P. Verheyen, et al., “A 70nm Vertical Si/Si(1-X)Gex
Heterojunction pMOSFET with Reduced DIBL Sensitivity for VLSI Applications," VLSI Symposium, pp. 19, 1999.
[23] N. Yasutake, et al.,"A High Performance pMOSFET with Two-step Recessed SiGe-S/D Structure for 32nm node and Beyond"IEEE Solid-State Device Research Conference, pp.77-80 , 2006
[24] Q. Ouyang, et al.," Two-Dimensional Bandgap Engineering in a Novel
Si/SiGe pMOSFET With Enhanced Device Performance and Scalability,"IEEE Simulation of Semiconductor Processes and Devices, pp. 151-154,2000.
[25] S. S. Chung, et al., “N-Channel versus P-Channel Flash EEPROM Which one has better reliabilities", IEEE Annual International Reliability Physics Symposium, pp. 67-72, 2001.
[26] T. Ohnakado, et al., “Novel Electron Injection Method Using Band-to-Band Tunneling Induced Hot Electron (BBHE) for Flash Memory with a P-channel Cell" IEEE International Electron Device Meeting,
pp.279-282 , 1995.
[27] Kailash Gopalakrishnan, et al., “Novel Very High IE Structures Based on the Directed BBHE Mechanism for Ultra low-Power Flash Memories,"IEEE Electron Device Letters, Vol.26, pp. 212-215, 2005
[28] Verma, et al., "Reliability Performance of ETOX Based Flash Memory", International Reliability Physics Symposium, pp.158,1998.
[29] Haddad, et al., "Degradation Due to Hole Trapping in Flash Memory Cells", IEEE Electron Device Letters, Vol.10, No.3, P.117, 1989.
[30] Adam Brand, et al., "Novel Read Disturb Failure Mechanism Induced by Flash Cycling", International Reliability Physics Symposium, pp.127, 1993.
[31] Robert J. P. Lander, et al., “High Hole Mobilities in Fully-Strained Si(1-x)Gex Layers (0:3 < x < 0:4) and their Significance for SiGe pMOSFET Performance"IEEE Transactions on Electron Devices, Vol. 48, pp.1826-1832, 2001.
[32] Hang-Ting Lue, et al.,“Studies of the Reverse Read Method and Second-Bit Effect of 2-Bit/Cell Nitride-Trapping Device by Quasi-Two-Dimensional Model"IEEE Transactions on Electron Devices,Vol. 53, pp. 119-125, 2006.
[33] Simon Tam,Ping-Keung Ko, Chenming Hu, R.S. Muller ,"Lucky-electron model of channel hot-electron injection in MOSFETs."IEEE Transactions on Electron Device,Vol.31,Issue:9,P.1984,Setpember 1984.
[34] K. Hasnat,cC.-F.Yeap,S.Jallepalli,W.-K. Shih,S.A. Hareland,V.M.Agostinelli, ,Jr.,A.F.Tasch,, Jr.,C.M.Maziar,"A pseudo-lucky electron model for simulation of electron gate current in submicron NMOSFET's"IEEETransactions on Electron Device,Vol.43 Issue:8,Aug.pp.1264-1273,1996.
[35] M. Lenzlinger,E.H.Snow.,"Fowler-Nordheim tunneling into thermally grown SiO2",Journal of Applied Physics,40(1):278,tanuary 1969
[36] Chi Chang,Jih Lien.,"Corner-field induced drain leakage in thin oxide MOSFET's application.", IEEE-IEDM Tech. Dig.,P.714,December 1987.
[37] Szu-Yu Wang,Hang-Ting Lue,"Reliability and processing effects of bandgap engineered SONOS(BE-SONOS) flash memory",IEEE Annual International Reliability Physics Symposium, Phoenix, pp. 171-176,2007.
[38] S.M.,"Semiconductor Device Physics and Technology" 2rd edition ,2002.
[39] Jong Jin Lee,Xuguang Wang,Nan Lu and Dim-Lee Kwong “Theoretical and Experimental Investigation of Si Nanocrystal Memory Device With HfO2 High-K Tunneling Dielectric",IEEE Transcations on Electron Devices
Letter,pp.2067-2072,2003.
[40] T.Sugizaki,M.Ishidao,H.Minakata,"Novel Multi-bit SONOS Type Flash Memory using a High-k Charge Trapping Layer",Symposium on VLSI Technology Digest of Technical Papers,pp.27-28,2003.
[41] Xuguang Wang and Dim-Lee Kwong, Senior Member, “A Novel High-k SONOS Memory Using TaN/Al2O3/Ta2O5/HfO2/Si Structure for Fast Speed and Long Retention Operation" IEEE Transaction on Electron Device, VOL.53, NO. 1, January 2006.
[42] Yan Ny Tan, Student Member, IEEE, Wai Kin Chim, Senior Member, IEEE,Wee Kiong Choi, Senior Member, IEEE,Moon Sig Joo, and Byung Jin Cho,Senior Member, IEEE ," Hafnium Aluminum Oxide as Charge Storage and Blocking-Oxide Layers in SONOS-Type NonvolatileMemory for High-Speed Operation ," IEEE Transaction on Electron Device, VOL.53, NO. 4,pp.654-662, April 2006.
[43] J.Buckley,M.Bocquet,G.Molas,M.Gely,“In-depth Investigation of Hf-based High-k Dielectrics as Strorage Layer of Charge-Trap NVMs",2006
[44] 劉得強, “Operation Characteristic of Charge-Trapping-Type Flash Memory Device with Charge-Trapping Layer of Stacked Dielectrics",國立清華大學電子工程研究所,2008
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