臺灣博碩士論文加值系統

本論文提出了一種精巧的正子斷層造影儀之數位信號處理模組，並成功地將此模組實現於單一FPGA晶片上，達到模組的微型化以及系統的硬體電路體積縮小的目標。針對使用「Pulse trigger」以及「timing-mark」為時間資訊信號的兩種前級偵檢器，分別實現適合之時間符合計算電路來因應。
此外，在本數位信號處理模組中，數位即時堆疊減算校正電路的設計與實現解決了因為事件堆疊而產生的能量累積問題，還原出無堆疊的能量信號，並經由將時間資訊信號延遲，恢復已還原之無堆疊能量信號與事件發生時間的時序同步。
在實測與驗證上，本論文以4對4前端偵檢器配置架構進行整體數位信號處理模組之模擬，成功判別符合事件並將代表正子事件資訊之配對信號與相對應事件位置以及能量信號合併，輸出至後級資料傳輸介面。
根據測試之結果，論文並將比較使用「Pulse trigger」以及「timing-mark」為時間資訊信號的數位信號處理模組之間的差異以及優劣。

第一章 序論….…………………………………………………...……...1
1.1 PET正子斷層造影介紹………………………………………..1
1.2 研究緣起與目的………………………………...……………...3
1.3 正子/單光子雙用途乳房造影儀系統架構…………………….5
1.4 論文整體架構……………………………………...…………...9
第二章 數位信號處理與FPGA平台……………………..…………...10
2.1 文獻回顧……………………………...……………………….10
2.2 數位信號處理模組之架構………………….………………...17
2.3 FPGA平台介紹…………………………………………….…20
第三章 數位信號處理模組之設計…………………………………….22
3.1 事件堆疊…..……………………….…………….…................22
3.2 HYPER演算法………………………………………………..24
3.3 即時堆疊減算校正電路………………………………………28
3.3.1 即時堆疊減算校正電路之結構介紹……...…………29
3.3.2 即時減算校正單元…………………………...………31
3.4 時間符合計算電路……………………………………………33
3.4.1 總符合事件計算單元…………………...……………35
3.4.2 延遲電路………………………………………..…….38
3.4.3 符合事件資料傳輸控制電路………………………...39
第四章 數位信號處理模組之實現與測試…………..…..………….…41
4.1 數位即時堆疊減算校正電路之實現………………………....41
4.1.1 即時減算校正單元…………………..……………….42
4.1.2 時序控制電路………………………...………………46
4.1.3 資料儲存單元…………………………...……………48
4.2 時間符合計算電路之實現………………………...………….50
4.2.1 符合事件計算單元……………………...……………52
4.2.2 時序控制電路……………………….………………..54
4.2.3 延遲電路………………………….…………………..55
4.2.4 資料儲存單元……………….…….………………….56
4.2.5 符合事件資料傳輸控制電路……………………..….57
4.3 數位即時堆疊減算校正電路之測試……………..…………..60
4.4 事件符合計算電路之測試………………….………………...65
4.4.1 延遲電路之測試……………………..……………….65
4.4.2 總符合事件計算之測試…………………...…………69
4.4.3 符合事件資料傳輸控制電路之測試………………...73
4.5 數位信號處理模組之測試………………………..…………..76
第五章 結論與未來展望………………………..……………………...84
5.1 結論…………………………………………………...……….84
5.2 未來展望………………………………………………………86
參考文獻………………………..…………………………….…………..87

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