(3.236.222.124) 您好!臺灣時間:2021/05/13 21:26
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果

詳目顯示:::

我願授權國圖
: 
twitterline
研究生:符敏兒
研究生(外文):PHU MAN NHI
論文名稱:以改良式布斯-華勒斯樹乘法器實現管線式浮點運算器
論文名稱(外文):Design and Implementation of a Pipelined Floating Point Unit with Modified Booth-Wallace Tree Multiplier
指導教授:呂紹偉
指導教授(外文):Shao-Wei Leu
學位類別:碩士
校院名稱:國立臺灣海洋大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:96
語文別:中文
論文頁數:72
中文關鍵詞:IEEE 754布斯-華勒斯樹乘法器浮點運算器
外文關鍵詞:IEEE754Booth-Wallace Tree MultiplierFPU
相關次數:
  • 被引用被引用:0
  • 點閱點閱:560
  • 評分評分:系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
在影像和語音等訊號處理過程中,乘法運算扮演非常重要的角色。因此,乘法器之運算速度與低功率消耗之特性是電路設計者必須重視的課題。本論文以浮點運算之乘法器作為設計主軸,採用改良式布斯-華勒斯樹乘法器(Modified Booth-Wallace Tree Multiplier)以提升運算速度,我們針對進位傳遞延遲的缺點進行改善並且提出一個新的布斯-華勒斯樹乘法器架構。對於所提出的浮點運算架構則以Verilog硬體描述語言撰寫,透過Xilinx-VLXS500及Vericomm輔助軟體進行驗證浮點運算器功能之正確性,接著經由Design Compile進行完整之電路合成與最佳化,得知整體電路工作頻率可達400MHz時脈速率。








關鍵詞:IEEE-754,布斯-華勒斯樹乘法器,浮點運算器 。
致謝詞..................................................I
摘要...................................................II
Abstract..............................................IV
目錄...................................................V
圖目錄.............................................. VIII
表目錄.................................................X
第一章 緒論.............................................1
1.1 研究動機與目的..................................1
1.2 研究方法............................................2
1.3 論文內容提要........................................2
第二章:乘法器的設計原理與探討.............................4
2.1 IEEE754浮點數標準格式...........................4
2.2 浮點運算器......................................5
2.3 乘法的計算原理說明..............................7
第三章:乘法器的相關研究..................................8
3.1 循序式乘法器....................................9
3.2 陣列式乘法器....................................11
3.3 改良式布斯-華勒斯樹乘法器.........................13
3.3.1 部份乘積產生模組...........................14
3.3.1.1 布斯演算法..........................15
3.3.1.2 二補數表示法........................18
3.3.1.3 改良式布斯演算法..................20
3.3.2 華勒斯樹模組..............................24
3.3.2.1 壓縮器...........................25
3.3.3 最終加法器模組............................28
第四章:改良式佈斯-華勒斯樹乘法器之電路設計................31
4.1 改良式布斯演算法...............................32
4.2 華勒斯樹......................................40
4.2.1 Carry Save Adder設計原理................41
4.2.2 3:2 Compressor原理說明..................42
4.3 前瞻進位加法器.................................44
4.3.1 漣波進位加法器...........................44
4.3.2 前瞻進位加法器...........................45
第五章:浮點運算之整體電路設計...........................50
5.1 符號位元..........................................51
5.2 指數..............................................52
5.3 正規化............................................53
5.4 捨位..............................................55
5.5 後正規化..........................................58
第六章:模擬與驗證......................................59
6.1 補數型態之比較................................60
6.2 布斯編碼與部份乘積產生模組之比較................61
6.3 乘法器之比較.................................62
6.4 FPGA模擬與驗證................................65
6.5 效能分析......................................67
第七章:結論...........................................69
參考文獻..............................................70
[1] IEEE Standard for Binary Floating-Point Arithmetic, IEEE Press, 1985.
[2] B.Parhami, Computer Arithmetic: Algorithms and Hardware Design. Oxford Press, 2000.
[3] I.Koren, Computer Arithmetic Algorithms. Prentice Hall, 1993.
[4] W.-C. Yeh, and C.-W. Jen, “High-Speed Booth Encoded Parallel Multiplier Design,” IEEE Trans. Computers, vol. 49, no. 7, pp. July 2000.
[5] P.F. Stelling, C.U. Martel, V.G. Oklobdzija, and R.Ravi, “Optimal Circuits for Parallel Multipliers,” IEEE Trans. Computers, vol. 47, no. 3, pp.273-285, March 1998.
[6] V.G.Oklobdzija, D.Villeger, and S.S.Liu, “A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach,” IEEE Trans. Computers, vol. 45, no. 3, pp. March 1996.
[7] Lakshmanan, M.Othman, and M.A.M.Ali, “High Performance Parallel Multiplier Using Wallace-Booth,” IEEE International Conference on Semiconductor Electronics, pp. 433-436, 2002.
[8] A.D.Booth, “A Signed Binary Multiplication Technique”, Quarterly Journal of Mathematics, vol.4, pp.2, 1951.
[9] O.-L.MacSorley, “High Speed Arithmetic in Binary Computers,” Proc. IRE, vol. 49, Jan. 1961.
[10] C.S.Wallace, “A Suggestion for a Fast Multiplier,” IEEE Trans. Computers, vol. 13, no. 2, pp. 14-17, Feb. 1964.
[11] J.Um and T.Kim, “An Optimal Allocation of Carry-Save-Adders in Arithmetic Circuits,” IEEE Trans. Computers, vol. 50, no. 3, pp. 215-233, March 2001.
[12] B.Parhami, Computer Arithmetic Algorithms and Hardware Designs. Oxford Press, 2000.
[13] A.Wu, K.C.Tang, and C.K.Ng, “Pipelined Modified Booth Multiplication,” IEEE International Conference on Circuit and System, pp. 51-53, 1998.
[14] M.S.Elrabaa, I.S.Abu-Khater, and M.I.Elmasry, Advanced Low-Power Digital Circuit Techniques, Kluwer Aademic Publishers, 1997.
[15] M.J.Flynn, S.F.Oberman, Advanced Computer Arithmetic Design. John Wiley & Sons, 2001.
[16] N.Ohkubo, M.Suzuki, T.Shinbo, T.Yamanaka, A.Shimizu, K.Sasaki, and Y.Nakagone, “A 4.4 ns CMOS 54×54-b Multiplier Using Pass-Transistor Multiplexer,” IEEE Journal of Solid-State Circuits, vol. 30, no. 3, pp. 251-257, March 1995.
[17] K.Yano, T.Yamanaka, T.Nishida, M.Saitoh, K.Shimohigashi, and A. Shimizu, “A 3.8-ns CMOS 16×16-bit Multiplier Using Complementary Pass-transistor Logic,” Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 10.4.1-10.4.3, May 1989.
[18] G.Goto, A.Inoue, R.Ohe, S.Kashiwakura, S.Mitarai, T.Tsuru, and T. Izawa, “A 4.1 ns Compact 54×54-b Multiplier Utilizing Sign Select Booth Encoders,” IEEE Journal on Solid-State Circuit, vol. 32, no.11, pp. 1671-1681, Feb. 1997.
[19] K.-S.Cho, J.-O Park, J.-S.Hong, and G.-S.Choi, “54×54-bit Radix-4 Multiplier Based on Modified Booth Algorithm,” The 2003 Great Lakes Symposium on VLSI, pp. 233-237, 2003.
[20] 鄭琇文, “Design of a Carry-Propagation-Free Floating Point Multiplication Unit Based on a Novel Array Multiplier. 逢甲大學資訊工程學系碩士論文 June. 2001.
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
系統版面圖檔 系統版面圖檔