臺灣博碩士論文加值系統

本論文提出一個可防止掃描測試攻擊之安全測試封套，此技術使用安全機制來保護核心電路之主要輸入端與內部掃描鏈輸出入端。此安全架構只允許授權者執行所有測試運作，並需透過安全控制器來驗證測試圖樣是否相同於測試封套密鑰。而測試封套密鑰是由安全封套周邊單元所構成之線性回授位移暫存器(LFSR)所產生。另外此架構對於AES電路將增加約5%之面積成本，但可提供之高安全複雜度(2256)。在系統晶片內此安全架構將維持IEEE 1500標準測試封套之特性，且不需要更動系統晶片內嵌之核心電路。本論文實作安全測試封套之編譯與驗證之自動化軟體，其提升包覆測試封套核心電路之安全性，並可生成測試樣板來驗證安全測試封套之功能及核心電路。另外也實作一個使用者介面平台，整合安全測試封套與IEEE 1500標準測試封套之編譯與驗證軟體，提供指令模式之設計流程來輔助設計者設計與驗證封套架構。

This thesis presents a new secure test wrapper (STW) design for preventing scan-based attack. The technique provides a secure mechanism to protect primary inputs and scan in/out of internal scan chains in IP core. The secure architecture allows only authorized user to execute all test operation by using secure controller to verify whether test pattern is identical to test wrapper key. The test wrapper key is generated by linear-feedback shift register (LFSR) that is constructed from secure wrapper boundary cell. Experimental results on AES show that STW provides very high security (2256) for a small area overhead (approximately 5%). The architecture is compatible to IEEE 1500 standard and there is no need to modify the embedded IP core in System on Chip (SOC). An automatic compiler and validation tool for secure test wrapper is implemented. The user interface platform that includes compiler and validation tool of secure test wrapper and standard test wrapper is also implemented.

摘要 i
Abstract ii
目錄 iii
圖目錄 v
表目錄 vii
第一章 序論 1
1.1 論文背景與動機 1
1.2 技術與論文貢獻 3
1.3 論文組織 5
第二章 論文相關背景與研究 6
2.1 IEEE 1500標準測試封套概述 6
2.2.1 封套指令暫存器與封套串列協定 8
2.2.2 封套周邊暫存器與封套旁通暫存器 10
2.2.3 核心測試語言(Core Test Language) 12
2.3 相關研究 13
2.3.1 鏡子密鑰暫存器(mirror key registers, MKR)之安全掃描技術 15
2.3.2 擾亂掃描鏈之相關研究 16
2.3.3 嵌入額外硬體及測試密鑰之相關研究 17
2.3.4 其他相關研究 21
第三章 安全測試封套架構 24
3.1 安全測試封套之硬體架構 24
3.1.1 安全控制器之架構 27
3.1.2 安全封套單元之架構 30
3.1.3 支援接腳共用之安全封套單元 36
3.1.4 指令暫存器與封套介面訊號解碼之更新 39
3.1.5 安全測試封套之開鎖流程 40
3.2 安全測試封套之複雜度 42
3.3 安全測試封套之測試 47
3.3.1 安全控制器之測試 48
3.3.2 安全封套暫存器之測試 52
第四章 軟體實作與實驗結果 54
4.1 安全測試封套編譯與驗證軟體實作 54
4.1.1 種子解算器 55
4.1.2 安全測試封套編譯器 59
4.1.3 安全測試封套驗證軟體 62
4.1.4 安全測試封套之CTL產生器 64
4.2 整合測試封套編譯與驗證之設計流程 66
4.2.2 整合設計流程 68
4.2.1 使用者介面實作 70
4.2.3 整合設計之指令功能 72
4.3 安全測試封套之面積比較 73
4.2.1 AES電路之安全測試封套面積比較 74
4.2.2 ISCAS電路之安全測試封套面積比較 75
第五章 討論與未來工作 77
5.1 提升LFSR之複雜度 77
5.2 比較其他安全架構 78
5.3 未來工作 78
第六章 結論 80
參考文獻 81
附錄A 進階加密標準(AES)概述 85

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