|
[1] http://www.eecs.mit.edu/100th/images/Whirlwind-op.ctrl-site.html/. [2] I. E. Sutherland, Sketchpad, aMan-Machine Graphical Communication System, Ph.D. thesis, Massachusetts Insititute of Technology, January 1963. [3] http://www.pong-story.com/. [4] http://www.nvidia.com/. [5] Tomas Akenine-M¨oller and Jacob Str¨om, “Graphics for the masses: A hardware rasterization architecture for mobile phones,” ACM Transactions on Graphics, vol. 22, no. 3, pp. 801–808, July 2003. [6] Richard Fromm, Stylianos Perissakis, Neal Cardwell, Christoforos E. Kozyrakis, Bruce McGaughy, David A. Patterson, Thomas E. Anderson, and Katherine A. Yelick, “The energy efficiency of IRAM architectures,” in 24th Annual International Symposium on Computer Arhchitecture, 1997, pp. 327–337. [7] John D. Owens, Ujval J. Kapasi, Peter Mattson, Brian Towles, Ben Serebrin, Scott Rixner, and William J. Dally, “Media processing applications on the Imagine stream processor,” in Proceedings of the IEEE International Conference on Computer Design, 2002, pp. 295–302. [8] B. Khailany, “A programmable 512 gops stream processor for signal, image, and video processing,” in ISSCC Dig. Tech. Papers. IEEE, February 2007, pp. 272–273. [9] E. Catmull, A Subdivision Algorithm for Computer Display of Curved Surfaces, Ph.D. thesis, University of Utah, December 1974. [10] B.-T. Phong, “Illumination for computer generated pictures,” Commun. ACM, vol. 18, no. 6, pp. 311–317, 1975. [11] Lance William, “Pyramidal parametrics,” in Proceedings of ACM SIGGRAPH, 1983. [12] John Kessenich, “The OpenGL ES shading language,” http://www.opengl.org. [13] W. F. Engel, Ed., Direct3D ShaderX: Vertex and Pixel Shader Tips and Tricks, Wordware Publishing, Inc., 2002. [14] David Blythe, “The direct3d 10 system,” ACM Transactions on Graphics (SIGGRAPH’06), vol. 25, no. 3, pp. 724–734, July 2006. [15] http://www.gamedev.net/reference/articles/article1820.asp. [16] M. D. McCool, J. Ang, and A. Ahmad, “Homomorphic factorization of BRDFs for high-performance rendering,” in Proceedings of the 28th annual conference on Computer graphics and interactive techniques( SIGGRAPH ’01), New York, NY, USA, 2001, pp. 171–178, ACM Press. [17] Philippe Beaudoin and Juan Guardado, ”Non-integer Power Function on the Pixel Shader”, ShaderX, Wordware Inc., second edition, 2002. [18] Philippe Beaudoin and Juan Guardado, ”Non-Photorealistic Rendering with Pixel and Vertex Shaders”, ShaderX, Wordware Inc., 2002. [19] Jiawen Chen, Michael I. Gordon, William Thies, Matthias Zwicker, Kari Pulli, and Fredo Durand, “A reconfigurable architecture for load-balanced rendering,” in Proceedings of the ACM SIGGRAPH/EUROGRAPHICS conference on Graphics hardware (HWWS ’05), Aire-la-Ville, Switzerland, Switzerland, 2005, pp. 71 – 80, Eurographics Association. [20] Eric Haines, “An introductory tour of interactive rendering,” in Computer Graphics and Applications. IEEE, 2006, pp. 76–87. [21] John H. Reif and Sandeep Sen, “An efficient output-sensitive hidden surface removal algorithm and its parallelization,” in Symposium on Computational Geometry, 1988, pp. 193–200. [22] Ziyad S. Hakura and Anoop Gupta, “The design and analysis of cache architecture for texture mapping,” in Proceedings of 24th International Symposium of Computer Architecture, 1997, pp. 108–120. [23] Homan Igehy, Matthew Eldridge, and Kekoa Proudfoot, “Prefetching in a texture cache architecture,” in Proceedings of the ACM SIGGRAPH/ Eurographics conference on Graphics hardware, 1998. [24] Jacob Str¨om and T. Akenine-M¨oller, “iPACKMAN: high-quality, lowcomplexity texture compression for mobile phones,” in Proceedings of the ACM SIGGRAPH/Eurographics conference on Graphics hardware, 2005, pp. 63–70. [25] KoenMeinds and Bart Barenbrug, “Resample hardware for 3D graphics,” in Proceedings of the ACM SIGGRAPH/Eurographics conference on Graphics hardware, 2002, pp. 17–26. [26] Joel McCormack and Robert McNamara, “Tiled polygon traversal using half-plane edge functions,” in Proceedings of the ACM SIGGRAPH/ EUROGRAPHICS workshop on Graphics hardware. 2000, pp. 15– 21, ACM. 102 [27] Juan Pineda, “A parallel algorithm for polygon rasterization,” SIGGRAPH Computer Graphics, vol. 22, no. 4, pp. 17–20, 1988. [28] M. McCool, C. Wales, and K. Moule, “Incremental and hierarchical hilbert order edge equation polygon rasterization,” in Proceedings of the ACM SIGGRAPH/ EUROGRAPHICS workshop on Graphics hardware. 2001, pp. 65– 72, ACM. [29] Bo Han and Bingfeng Zhou, “Efficient video decoding on gpus by point based rendering,” in Proceedings of the ACM SIGGRAPH/Eurographics conference on Graphics hardware, 2006, pp. 79–86. [30] Francis Kelly and Anil Kokaram, “Fast image interpolation for motion estimation using graphics hardware,” in Proceedings of the IS&T/SPIE Electronic Imaging, 2004, pp. 184–194. [31] Draft ITU-T Recommendation H.263, Video Coding for Low Bitrate Communication, ITU, 1995. [32] Joint Video Team(JVT) of ISO/IEC MPEG and ITU-T VCEG, Draft ITUT recommendation and final draft international standard of joint video specification(ITU-T Rec. H.264/ISO/IEC 14496-10 AVC), JVTG050, 2003. [33] Robert M. Haralick and Linda G. Shapiro, Computer and Robot Vision, AddisonWesley Longman Publishing Company, 1992. [34] Ruigang Yang and Greg Welch, “Fast image segmentation and smoothing using commodity graphics hardware,” Journal of Graphics Tools, vol. 7, no. 4, pp. 91–100, Dec. 2002. [35] R. Fernando and M. J. Kilgard, The Cg Tutorial, Addison-Wesley, 2003. [36] You-Ming Tsao, Chih-Hao Sun, Yu-Cheng Lin, Ka-Hang Lok, Chia-Jung Hsu, Shao-Yi Chien, and Liang-Gee Chen, “A 26mW 6.4 GFLOPS multi103 core stream processor for mobile multimedia applications,” in Proceedings of Symposium on VLSI Technology and Circuits, 2008. [37] Shao-Yi Chien, Yu-Wen Huang, Bing-Yu Hsieh, Shyh-Yih Ma, and Liang- Gee Chen, “Fast video segmentation algorithm with shadow cancellation, global motion compensation, and adaptive threshold techniques,” IEEE Transactions on Multimedia, vol. 6, no. 5, pp. 732–748, Oct. 2004. [38] Andrew C. Beers, Maneesh Agrawala, and Navin Chaddha, “Rendering from compressed textures,” in Proceedings of ACM SIGGRAPH, 1996. [39] Edward J.Delp and O. Robert Michell, “Image compression using block truncation coding,” IEEE Transactions on Communications, vol. 27, no. 9, pp. 1335–1342, Sept. 1979. [40] Graham Campbell, Thomas A. DeFanti, Jeff Frederiksen, Stephen A. Joyce, and Lawrence A. Leske, “Two bit/pixel full color encoding,” in Proceedings of ACM SIGGRAPH, 1986, vol. 20, pp. 215–223. [41] Konstantine I. Iourcha, Krishna S. Nayak, and Zhou Hong, “System and method for fixed-rate block-based image compression with inferred pixel values,” in US Patent 5,956,431, 1999. [42] Simon Fenney, “Texture compression using low-frequency signal modulation,” in Proceedings of the ACM SIGGRAPH/Eurographics conference on Graphics hardware, 2003, pp. 84–91. [43] J. Str¨om and T. Akenine-M¨oller, “PACKMAN: texture compression for mobile phones,” in Sketches Program at SIGGRAPH, 2004. [44] Jacob Str¨om and Martin Pettersson, “ETC2: texture compression using invalid combinations,” in Proceedings of the ACM SIGGRAPH/Eurographics conference on Graphics hardware, 2007, pp. 49–54. 104 [45] Anton V. Pereberin, “Hierarchical approach for texture compression,” in Proceedings of GraphiCon’99, 1999, pp. 195–199. [46] Jerzy Stachera and Przemyslaw Rokita, “Hierarchical texture compression,” in International Conferences in Central Europe on Computer Graphics, Visualization and Computer Vision, 1997, pp. 108–120. [47] David S. Taubman and MichaelW. Marcellin, JPEG2000: Image Compression Fundamentals, Standards, and Practice, Kluwer Academic Publishers, 2002. [48] J.-H Woo, “A 152mw/195mw multimedia processor with mpeg/h.264/jpeg and fully programmable 3d graphics for mobile applications,” in Symposium on VLSI Circuits Dig. Tech. Papers. IEEE, January 2007, pp. 220–221. [49] B.-G Nam, “A 52.4mw 3d graphics processor with 141mvertices/s vertex shader and 3 power domains of dynamic voltage and frequency scaling,” in ISSCC Dig. Tech. Papers. IEEE, February 2007, pp. 278–279. [50] U. Kapasi, “Programmable stream processors,” Computer, vol. 36, no. 8, pp. 54–62, August 2003. [51] I. Buck, “Brook for gpus: stream computing on graphics hardware,” ACM Transactions on Graphics (SIGGRAPH’04), vol. 23, no. 3, pp. 777–786, August 2004. [52] Microsoft Corporation, DirectX 10.0 SDK, Microsoft Corporation, Redmond, Washington, 2006. [53] Jeong-Ho Woo, Ju-Ho Sohn, Hyejung Kim, Jongcheol Jeong, Euljoo Jeong, Suk Joong Lee, and Hoi-Jun Yoo, “A 152mW/195mWmultimedia processor with MPEG/H.264/JPEG and fully programmable 3D graphics for mobile applications,” in Proceedings of Digest of Technical Papers of the 2007 IEEE International Solid-State Circuits Conference (ISSCC 2007), 2007. 105 [54] Byeong-Gyu Nam, Jeabin Lee, Kwanho Kim, Seung Jin Lee, and Hoi-Jun Yoo, “A 52.4mW 3D graphics processor with 141Mvertices/s vertex shader and 3 power domains of dynamic voltage and frequency scaling,” in Proceedings of Digest of Technical Papers of the 2007 IEEE International Solid- State Circuits Conference (ISSCC 2007), 2007.
|