臺灣博碩士論文加值系統

近年來由於消費性產品大幅增加，如手機、MP3 Player…等，其音頻訊號自然為主要處理對象。如何將音頻轉換成數位訊號或數位訊號轉換成類比訊號且可保持高解析度？其三角積分調變器，為主要解決方式。

此論文中將探討聯電90奈米製程下音訊類比數位轉換器，其測試晶片驗證下，可得到96dB的動態範圍(DR)及-93dB 的總諧振雜訊失真加雜訊(THD+N)的結果。並且在使用2.5伏的供應電源時，需要消耗1毫安培的電流。在此調變器中使用了動態調整誤差器，其可將數位到類比轉換過程所產生的誤差作二階的雜訊抑制，並且可以將因訊號功率小所產生的許多單頻雜訊移出訊號頻帶之外。

In recent years, increases by huge grow up in the consuming products such as cell-phone and MP3 Player. How to change audio signal into digital signal processing and keep high resolution to overcome limitations from the poor component matching and reduced power supply levels that accompany these technologies? Sigma-Delta (ΔΣ) modulations are well-suited to the implementation of analog interfaces in digital communication and signal processing systems.

A second-order multi-bit ΔΣ modulator for audio analog-to-digital converter is presented. The design uses a second-order mismatch-shaping algorithm to reduce the mismatch requirements of the DAC unity elements and optimized to minimize the delay introduced in the feedback loop. At an oversampling ratio of 64, an experimental implementation of the modulator integrated in a 90-nm CMOS technology that achieves a 96-dB dynamic range and -93-dB THD+N at a Nquist rate of 48-KHz. The power consumption of the converter is 2.5-mW, from a single 2.5-V supply voltage.

Table of Contents



Table of Contents I
List of Figures III
List of Tables VII


Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Thesis Organization 2

Chapter 2 Fundamentals of Sigma-Delta Converter 5
2.1 Introduction 5
2.2 Data Converter Performance Metrics 6
2.3 Quantization Noise Analysis 6
2.4 Oversampling 8
2.5 First-Order Sigma-Delta Modulator 10
2.6 Second-Order Sigma-Delta Modulator 12
2.7 High-Order Sigma-Delta Modulator 13
2.8 Multi-Stage (Cascade, MASH) Sigma-Delta Modulator 14
2.9 Multi-Bit Sigma-Delta Modulator 16
2.10 Summary 19

Chapter 3 Design and Implementation of a Multi-Bit Sigma- Delta Modulator 21
3.1 Sigma-Delta Modulator Architecture 21
3.1.1 Modulator Coefficients 22
3.1.2 5-Bit Quantizer 24
3.1.3 5-Bit SC Digital-to-Analog Converters 26
3.1.4 Tree-Structured Second-Order Mismatch-Shaping 27
3.2 Analysis Circuit Noidealities 30
3.2.1 Finite Operational Amplifier Gain and GBW 30
3.2.2 Minimum Input Capacitor 34
3.2.3 Minimum Input Switches 35
3.2.4 Noise Effect in Stray-Insensitive SC Integrator 38
3.3 OTA Topology Selection 40
3.4 Summary 41

Chapter 4 Circuit Implementation 43
4.1 Introduction 43
4.2 Sampling Circuit 43
4.3 Miller CMOS Operational Amplifier 44
4.4 SC Integrator Circuit 46
4.5 Voltage Comparator 47
4.6 5-Bit Flash ADC 48
4.7 Wide-Swing Constant-Gm Bias Circuit 49
4.8 The Simulation Results of Multi-Bit Second-Order ΔΣ Modulator 50
4.9 Layout and Floorplan 54
4.10 Summary 55

Chapter 5 Test and Experimental Results 57
5.1 Introduction 57
5.2 Test Setup 57
5.2.1 Test Equipment 57
5.2.2 Print Circuit Board Design 58
5.3 Experimental Results 59
5.4 Summary 60

Chapter 6 Conclusions 61
6.1 Conclusions 61
6.2 Future Works 61

Bibliography 65

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