臺灣博碩士論文加值系統

The world is facing a common problem that the number of elderly people is increasing. Most of the senior citizen suffers from a chronic disease that should be monitored and observed for a long term. Therefore, Personal home care services become a new developing market. By using the personal home care system, the patient’s vital signals can be measured at any time any place at home so that the measuring devices should be portable and possess the ability of short-range wireless communication. As a result, short range, low data rates, low cost and low power dissipation are the important issues of the receiver. For these specifications, three kinds of receivers and a high integration of the transceiver are proposed in this dissertation. Four chips are implemented and fabricated in standard 0.35-um CMOS process in the thesis.

The first chip is a self-mixing OOK receiver which can operate at multiband (433 MHz, 868 MHz, 1.8 GHz and 2.4 GHz). A wide-bandwidth limiting amplifier is used to amplify the input RF signal. In the limiting amplifier, the output impedance of the gain stages possesses the inductive behavior. Besides, the self-mixing technique realized by the voltage multiplier is used for demodulation.

The second chip is a super-regenerative receiver with two different topologies. The proposed self-mixing technique is employed for envelope detection in the two topologies. Besides, not alike the conventional super-regenerative receiver, a current-reuse VCO utilized as the super-regenerative oscillator is controlled by the voltage DAC in the second topology.

To achieve greater immunity to noise, interference, and multi-path distortion, a spread spectrum receiver is proposed. Only the chirp generator which is traditionally realized by the SAW filter in the chirp spread spectrum system is developed in the thesis. The carrier frequency of the chirp signals is linearly increased from 875MHz to 925MHz (up-chirp) or decreased from 925MHz to 875MHz (down-chirp) by a step of 6.25MHz. Without using the SAW filter that is often not implemented in the CMOS process, higher integration can be achieved.

Finally, a 915MHz ISM band transceiver is presented. By varying the output of the frequency synthesizer, the chip can be used as a transmitter or a receiver, which is very attractive. The integration of the transceiver reduces not only the system power consumption but also the overall system cost, which would be beneficial to the development of the Personal home care services applications.

Chinese Abstract ------------------------------------------------------------------------------I
English Abstract ------------------------------------------------------------------------------III
Table of Contents -----------------------------------------------------------------------------V
List of Figures ---------------------------------------------------------------------------------IX
List of Tables ---------------------------------------------------------------------------------XV
Chapter 1 Introduction ---------------------------------------------------------------------1
1.1 Motivation --------------------------------------------------------------------------------1
1.2 Thesis Organization ---------------------------------------------------------------------2
Chapter 2 Receiver Architectures ------------------------------------------------------5
2.1 Introduction ------------------------------------------------------------------------------5
2.2 Receiver architectures ------------------------------------------------------------------5
2.2.1 Super-Heterodyne Receiver ---------------------------------------------------5
2.2.2 Image-Rejection Receiver: Hartley and Weaver ----------------------------8
2.2.3 Homodyne Receiver: ----------------------------------------------------------10
2.2.4 Low –IF Receiver --------------------------------------------------------------13
2.3 Summary --------------------------------------------------------------------------------13
Chapter 3 A Monolithic Self-mixing OOK CMOS Receiver for Wireless Sensor Network -------------------------------------------------------------15
3.1 Introduction -----------------------------------------------------------------------------15
3.2 System Architecture -------------------------------------------------------------------15
3.3 Circuit implementation ----------------------------------------------------------------17
3.3.1 Low noise amplifier (LNA) --------------------------------------------------17
3.3.2 Limiting Amplifier (LA) -----------------------------------------------------21
3.3.3 Demodulator: voltage multiplier, low pass filter and comparator ------24
3.3.4 Output data buffer -------------------------------------------------------------26
3.4 Measurement results -------------------------------------------------------------------26
3.4.1 Input matching (S11) of LNA ------------------------------------------------27
3.4.2 Final output ---------------------------------------------------------------------28
3.4.3 Bit error rate (BER) of the receiver -----------------------------------------28
3.5 Summary --------------------------------------------------------------------------------31
Chapter 4 A 915 MHz Super-Regenerative Receiver with Self-mixing Technique -------------------------------------------------------------------33
4.1 Introduction -----------------------------------------------------------------------------33
4.2 Theory of Super-Regenerative Receiver --------------------------------------------33
4.3 The Proposed Receiver Architecture ------------------------------------------------38
4.3.1 System architecture -----------------------------------------------------------38
4.3.2 SAR Auto-Calibration --------------------------------------------------------39
4.3.3 Quench Mechanism -----------------------------------------------------------40
4.3.4 Timing diagram ----------------------------------------------------------------41
4.4 Circuit Implementation ----------------------------------------------------------------42
4.4.1 Building Blocks of the first topology ---------------------------------------42
4.4.1.1 Low noise amplifier (LNA) ---------------------------------------------42
4.4.1.2 Voltage Controlled Oscillator (VCO) ----------------------------------42
4.4.1.3 Demodulator: envelope detector, pre-amplifier and comparator ---44
4.4.1.4 Digital Controller --------------------------------------------------------45
4.4.1.5 Current Output Digital to Analog Converter (DAC) ----------------47
4.4.2 Building Blocks of the second topology ------------------------------------48
4.4.2.1 Voltage Controlled Oscillator (VCO) ----------------------------------49
4.4.2.2 Voltage DAC --------------------------------------------------------------50
4.5 Measurement Results ------------------------------------------------------------------50
4.5.1 The first topology --------------------------------------------------------------50
4.4.1.1 Low noise amplifier (LNA) ---------------------------------------------53
4.5.1.2 VCO ------------------------------------------------------------------------54
4.5.1.3 ICritical searching mode ---------------------------------------------------55
4.5.1.4 Signal detection mode ---------------------------------------------------56
4.5.1.5 BER ------------------------------------------------------------------------56
4.5.2 The second topology ---------------------------------------------------------58
4.5.2.1 LNA ------------------------------------------------------------------------59
4.5.2.2 VCO ------------------------------------------------------------------------59
4.5.2.3 Signal Detection mode --------------------------------------------------59
4.6 Summary --------------------------------------------------------------------------------61
Chapter 5 A Spread Spectrum Receiver with Chirp Technique for Channel Band 875MHz~925MHz --------------------------------63
5.1 Introduction -----------------------------------------------------------------------------63
5.2 Theory of the spread spectrum receiver ---------------------------------------------68
5.2.1 Basic Chirp Theory ------------------------------------------------------------69
5.2.2 Binary Orthogonal keying (BOK) ------------------------------------------70
5.3 The Proposed Receiver Architecture ------------------------------------------------70
5.3.1 Frequency planning of the chirp signal -------------------------------------72
5.3.2 The proposed receiver architecture ------------------------------------------73
5.3.3 The proposed architecture of the chirp generator -------------------------74
5.3.4 Frequency synthesizer: phase locked-loop (PLL) and direct digital synthesizer (DDS) ------------------------------------------------------------75
5.4 Circuit Implementation ---------------------------------------------------------------77
5.4.1 Direct digital synthesizer (DDS) --------------------------------------------77
5.4.2 Filter -----------------------------------------------------------------------------77
5.4.3 Buffer chain --------------------------------------------------------------------79
5.4.4 Tri-mode divider ---------------------------------------------------------------80
5.4.5 Passive mixer -------------------------------------------------------------------81
5.5 Simulation Results ---------------------------------------------------------------------82
5.5.1 DDS -----------------------------------------------------------------------------82
5.5.2 Filter -----------------------------------------------------------------------------83
5.5.3 Buffer chain --------------------------------------------------------------------86
5.5.4 Tri-mode divider --------------------------------------------------------------87
5.5.5 Passive mixer -------------------------------------------------------------------88
5.5.6 Chirp generator ----------------------------------------------------------------88
5.5.7 Layout and Die photo ---------------------------------------------------------88
5.8 Summary --------------------------------------------------------------------------------88
Chapter 6 A Wireless RF Transceiver with Fractional-N Frequency Synthesizer -------------------------------------------------------------------91
6.1 Introduction -----------------------------------------------------------------------------91
6.2 Theory ----------------------------------------------------------------------------------91
6.3 System Architecture -------------------------------------------------------------------92
6.3.1 Fraction-N frequency synthesizer -------------------------------------------92
6.3.2 Transmitter ---------------------------------------------------------------------94
6.3.3 Receiver -------------------------------------------------------------------------94
6.4 Circuit implementation ----------------------------------------------------------------96
6.5 Measurement Results -----------------------------------------------------------------96
6.5.1 Measurement of the frequency synthesizer --------------------------------97
6.5.2 Measurement of the transmitter with the RF carrier supplied by the frequency synthesizer -------------------------------------------------------98
6.5.3 Measurement of the receiver with the LO signal supplied by the frequency synthesizer -------------------------------------------------------99
6.5.4 Measurement of the transceiver --------------------------------------------100
6.6 Summary ------------------------------------------------------------------------------102
Chapter 7 Conclusion --------------------------------------------------------------------105
Appendix A -----------------------------------------------------------------------------------109
Appendix B -----------------------------------------------------------------------------------113
Reference --------------------------------------------------------------------------------------117

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