本篇論文實現一個在晶片上可自我測試弦波抖動的方法。藉由累積分布函數的概念去解析弦波抖動，而後應用後置運算來加強對製程飄移的容忍。我們使用現場可程式化邏輯閘陣列來實現所設計的電路並應用任意波型產生器來產生所需的抖動訊源。與商業用自動化量測儀器比較，我們量測到的頻率錯誤率低於0.1%。當抖動的訊源頻率操作在較低的頻域，所量測到的振幅錯誤率則少於5%。

This study is to implement an on-chip sinusoidal jitter testing technique for design for test (DfT) application. The proposed technique utilizes cumulative density function
(CDF) based method to track the sinusoidal jitter, and applies post processing to enhance the process variation tolerance. We use FPGA to achieve the designed circuit, and employ an arbitrary waveform generator to inject jittery signal. Compared with the commercial automatic test equipment, the error ratio of jitter frequency is within 0.1%. When the jitter operates in lower frequency, the error ratio of jitter amplitude is less than 5%.

致謝 i
中文摘要 ii
Abstract iii
1 Introduction 1
1.1 Motivation 1
1.2 Jitter Measurement with Test Equipment 1
1.3 Review of DfT/BIST Techniques 2
1.4 The Proposed Jitter Measurement Technique 2
1.5 Thesis Organization 3
2 Background 4
2.1 Jitter Definition 4
2.2 Jitter Categorization and Generation 6
2.3 Previous Measurement Method 9
3 The SJ Extraction Technique 15
3.1 Basic Idea 15
3.2 CDF-based Sampling 15
3.3 The SJ Extraction Architecture 16
3.4 The SJ Extraction Flow 17
4 FPGA Implementation of The SJ Extraction Circuit 21
4.1 The FPGA Platform 21
4.1.1 Features of CycloneTMEP1C20F400C7 21
4.1.2 Device Parameters 22
4.1.3 Development board 24
4.2 SJ Extraction Circuitry Implementation 24
4.3 FPGA Implementation 26
4.4 Tuning Multi Delay Taps 27
4.5 Jitter Generation 28
5 Experimental Results 30
5.1 Test Environment Setup 30
5.2 Jitter Source Measurement Results 32
5.3 Delay Line Measurement Results 32
5.4 Period Jitter Tracking Results 35
6 Conclusion 41
References 42

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