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研究生:張弘志
研究生(外文):Hung-Chih Chang
論文名稱:基材鰭式場效電晶體與鍺量子井場效電晶體之模擬研究
論文名稱(外文):Simulation Study of Bulk FinFET and Ge Quantum Well pFET
指導教授:劉致為
指導教授(外文):Chee-Wee Liu
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電機工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:96
語文別:英文
論文頁數:67
中文關鍵詞:場效電晶體基材鰭式場效電晶體臨界電壓量子井
外文關鍵詞:MOSFETBulk FinFETThreshold VoltageQuantum Well
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基材鰭式場效電晶體具有散熱佳,低製造成本,與傳統場效電晶體製程相容等優點。結合RCAT與三面閘極的結構展現非常優異壓制短通道的能力。在模擬結果顯示該結構具有良好的SS及DIBL的電性特徵。由於載子在完全空乏的鰭式通道流動,臨界電壓會受到鰭式通道的寬度及高度影響,必須重新修正。相較於RCAT 結構,基材鰭式場效電晶體對於凹槽深度及反向基板偏壓的變化較為不敏感。為了降低漏電流,在通道加上較高的參雜濃度,同時也會有較好控制能力。而汲極輕度參雜(LDD)被用來減低價帶至導帶的穿隧電流。同時,增加閘極-汲極氧化層厚度可以在犧牲少許控制能力的狀態下有效減低漏電流。
應用於未來高速元件的一種 Si-cap/Ge/Si 結構以模擬方式探討它的特性。Si-cap假設為完全張弛,而鍺通道層假設為完全應變。90-nm 平板矽場效電晶體一搬須要有HALO怖植以降低短通道效應。矽鍺異質結構造成的量子井可以將電洞侷限在鍺通道內。模擬結果顯示,相較於矽元件,此舉可以增加閘極的控制能力。Ge的BTBT性質在分析後放入計算中。不同的矽覆蓋層與鍺通道厚度所造成的漏流增減均進行模擬驗證
Bulk FinFET has advantages of heat dissipation, wafer cost, process compatibility and extendibility of conventional planar MOSFET technologies. The combination of recess channel array transistors (RCAT) technology and triple-gate in bulk silicon prove excellent SCEs control ability. It owns superior subthreshold slope (~70 mV/dec) and DIBL characteristics in simulation works. Due to the fully depleted fin channel, the subthrehold voltage is modified by not only channel doping but also the fin width and fin height. The saddle-like FinFET structure shows good immunity of electric characteristics of recess depth variation and reverse body bias comparing to RCAT structure. To integrate with DRAMs process, the leakage current must be suppressed. With higher channel doping, it reduces the Ioff current and subthreshold slope. By adopting LDD in S/D region, the band-to-band-tunneling generation is smaller. Also, increasing the thickness of gate-to-drain oxide, can help the leakage
suppression a lot but only a slightly control ability sacrifice.
A Si-cap/Ge/Si pFET structure based on 90-nm node for future high-speed transistor application is simulated. The Si-cap is assume to be relax and Ge layer is fully strained. For 90-nm node planar control-Si device, HALO implantation is necessary to reduce the SCEs. The Si-cap/Ge heterostructure results in the holes confinement in the quantum well, which provide better control ability comparing to control-Si device. The BTBT model for Ge is analyzed and put into simulation. The leakage due to smaller bandgap of Ge is examined by different Si-cap thickness and
Ge layer thickness.
Contents
List of Figures IV
List of Tables VI
Chapter 1 Introduction
1.1 Advantage of MOSFET scaling down 1
1.2 Planar Bulk-Si MOSFET Scaling Challenges 2
1.3 General Background For Bulk FinFET 4
1.4 General Background For Ge Quantum Well pFET 5
1.5 Reference 7
Chapter 2 Physical Models in Device
2.1 Introduction Of Numerical Simulator 9
2.2 Transport Equation 10
2.2.1 Governing Equations for Device Physics 10
2.2.2 Drift-Diffusion Model 11
2.3 Mobility Model 11
2.3.1 Introduction 12
2.3.2 Mobility Due to Lattice Scattering 13
2.3.3 Doping-Dependent Mobility Degradation 13
2.3.4 Mobility Degradation At Si-Insulator Interface 13
2.3.5 High Field Saturation 14
2.4 Quantization Model 15
2.4.1 Model Description 16
2.5 Generation and Recombination 17
2.5.1 Shockley-Read-Hall (SRH) 17
2.5.2 Band-To-Band-Tunneling Model 18
2.6 Reference 19
Chapter 3 Simulation Study of Bulk FinEFT
3.1 Motivation 22
3.2 Device Structure 22
3.3 Threshold Voltage, DIBL Definition 25
3.3.1 Threshold Voltage Definition 25
3.3.2 Drain Induced Barrier Lowering Definition 25
3.4 Bulk FinFET Recess Depth 26
3.4.1 Introduction 26
3.4.2 Threshold Voltage Variation With Recess Depth 26
3.5 Fin Width and Fin Height Variaiton 27
3.6 Bulk FinFET Reverse Body Bias 29
3.6.1 Introduction 29
3.6.2 Threshold Voltage Variation With Reverse Body Bias 29
3.6.3 DIBL Variation With Reverse Body Bias 30
3.7 Reference 31
Chapter 4 Leakage Analysis of Bulk FinFET
4.1 Introduction 33
4.2 GIDL and Junction Leakage 35
4.3 Channel Doping 37
4.4 Lateral and Vertical LDD Doping 37
4.5 Tox thickness 40
4.6 Reference 42
Chapter 5 Simulation Study of Heterojunction Effect on Ge Quantum Well pFETs
5.1 Introduction 44
5.1.1 Advantage Of Germanium MOSFET 44
5.1.2 Issues Of Germanium MOSFET 45
5.2 Device Structure 47
5.3 Physical Models and Parameters 49
5.4 Results and Discussion 52
5.4.1 Substhreshold Slope Modification of pFET 52
5.4.2 Cap Thickness Variation 55
5.4.3 Ge layer Thickness Variation 59
5.5 Reference 62
Chapter 6 Conclusions
6.1 Summary 65
6.2 Future Work 66
Chapter 1
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[6] Q. Ouyang, X. Chen, S. P. Mudanai, X. Wang, D. L. Kencke, Al F. Tasch, L.
F.Register, and S. K. Banerjee, “ A Novel Si/SiGe Heterojunction pMOSFET with
Reduced Short Channel Effects and Enhanced Drive Current,” IEEE Trans. Electron
Devices., vol. 47, no. 10, pp. 1943-1949, Oct. 2000.
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Quantum Simulation,” in IEDM Tech. Dig., 2003, pp. 471-474.
[8] H. Shang, J. O. Chu, X. Wang, P. M. Mooney, K. Lee, J. Ott, K. Rim, K. Chan,
K.Guarini, M. Ieong, “ Channel Design and Mobility Enhancement in Strained
Germanium Buried Channel MOSFETs, ” in 2004 Int. Symp. VLSI Tech. Dig., 2004, pp.204-205.
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Chapter 2
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Chapter 3
[1] Sung-Woong Chung et al., “Highly Scalable Saddle-Fin(S-Fin) Transistor for Sub-50nm DRAM Technology,” Symp. VLSI Tech. Dig., p. 40, 2006.
[2] Yong-Sung Kim et al., IEDM Tech. Dig., p. 315, 2005
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[6] “Local-Damascene-FinFET DRAM Integration with p+ Doped Poly-Silicon Gate
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[7] R. S. Muller and T. I. Kamins, Device Electronics for Integrated Circuits, 2nd ed. Hoboken, NJ: Wiley, 1986, p. 443.
[8] Narain Arora (2007). Mosfet Modeling for VLSI Simulation: Theory And Practice. World Scientific, p. 197, Fig. 5.14.

Chapter 4
[1] S.A. Parke, J.E. Moon, H.J.C.W. Wann, and P.K. Ko, “Design for suppression of gate induced drain leakage in LDD MOSFETs using a quasi-two-dimension analytical model,” IEEE Trans. Electron Devices, vol.39, no.7, pp.1564–1703, July 1992.
[2] G.A.M. Hurkx, H.C. De Graaf, and W.J. Kloesterman, “A new analytical
diode model including tunneling and avalanche breakdown,” IEEE Trans. Electron Devices, vol.39, no.9, pp.2090–2098, Oct. 1992.
[3] A. Schenk, “An improved approach to the Shockley-Read-Hall recombination
in inhomogeneous of space charge regions,” J. Appl. Phys., vol.71, no.7, pp.3339–3349, April 1992.
[4] A. Schenk, “Rigorous theory and simplified model of the band -to-band tunneling in silicon,” Solid-State Electron., vol.36, no.1, pp.19–34, Jan. 1993.
[5] G. Vincent, A. Chantre, and D. Bois, “Electric field effect on thermal emission of traps in semiconductor junctions,” J. Appl. Phys., vol.50, no.8, pp.5484–5487, Aug. 1979.
[6] J. Furlan, Z. Gorup, F. Smole, and M. Topic, “Modeling tunneling assisted generation-recombination rate in space charge region of a PN A.Si:H junction,” J. of Modeling and Simulation of Microsystems, vol.1, no.2, pp.109–114, Feb. 1999.
[7] Kyoung-Rok Han, Byung-Kil Choi, Tai-su Park, Euijoon Yoon, In-Young Chung and Jong-Ho Lee,” Device Design Consideration for 50nm Dynamic Random Access Memory Using Bulk FinFET,” J. J. Apply. Phys., Vol. 44, No. 4B, 2005, pp. 2176–2179

Chapter 5
[1] C. C. Yen, B. J. Chow, F. GAO, S. J. Lee, M. H. Lee, C. –Y. Yu, C. W. Liu, L. J.
tang, and T. W. Lee, “Electron Mobility Enhancement Using Ultra thin Pure Ge on Si
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[2] S. Sze, Physics of Semiconductor Devices, 2nd Ed., New York: Wiley, 1981.
[3] M. L. Lee and E. A. Fitzgerald, “Optimized strained Si/ strained Ge dual channel
heterostructures for high mobility P- and N- MOSFETs,” IEDM Tech. Dig., pp. 429-432, 2003.
[4] H. Shang, J. O. Chu, S. Bedell, E. P. Gusev, P. Jamison, Y. Zhang, J. A. Ott, M.
Copel, D. Sadana, K. W. Guarini, and M. Leong, “Selectively formed high mobility
strained Ge PMOSFETs for high performance CMOS,” IEDM Tech. Dig., pp.157-160, 2004.
[5] A. Satta, T. Janssens, T. Clarysse, E. Simoen, M. Meuris, A. Benedetti, I. Hoflijk, B.De Jaeger, C. Demeurisse, and W. Vandervorst, "P implantation doping of Ge:
diffusion, activation, and recrystallization," J. Vac. Sci. Technol. B, vol. 24, no. 1, pp.
494-498, Jan./Feb. 2006.
[6] O.J. Gregory, L.A. Pruitt, E.E. Crisman, C. Roberts, and P.J. Stiles, "Native oxides
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Soc., vol. 135, no. 4, pp. 923-929, Apr. 1988.
[7] K. Prabhakaran and T. Ogino, "Oxidation of Ge(100) and Ge( 11) surfaces: an UPS and XPS study," Surf Sci., vol. 325, pp. 263-271, Mar. 1995.
[8] W.A. Albers, E.W. Valyocsik, and P.V. Mohan, "Tetragonal germanium dioxide layers on germanium," J. Electrochem. Soc., vol. 113, no. 2, pp. 196-198, Feb. 1966.
[9] Q. Ouyang, X. Chen, S. P. Mudanai, X. Wang, D. L. Kencke, Al F. Tasch, L. F.
Register, and S. K. Banerjee, “ A Novel Si/SiGe Heterojunction pMOSFET with
Reduced Short Channel Effects and Enhanced Drive Current,” IEEE Trans. Electron
Devices., vol. 47, no. 10, pp. 1943-1949, Oct. 2000.
[10] A. Rahman, A. Ghosh, and M. Lundstrom, “Assessment of Ge n-MOSFET by Quantum Simulation,” in IEDM Tech. Dig., 2003, pp. 471-474.
[11] H. Shang, J. O. Chu, X. Wang, P. M. Mooney, K. Lee, J. Ott, K. Rim, K. Chan,
K.Guarini, M. Ieong, “ Channel Design and Mobility Enhancement in Strained
Germanium Buried Channel MOSFETs, ” in 2004 Int. Symp. VLSI Tech. Dig., 2004, pp. 204-205.
[12] K. Rim, J.L. Hoyt, and J. F. Gibbons, “Fabrication and analysis of deep submicron strained-Si n-MOSFETs,” IEEE Trans. Electron Devices, 2000, vol. 47, pp. 1406-1415, no. 7, July 2000.
[13] Donghyun Kim, Tejas Krishnamohan, Lee Smith, H.-S. Philip Wong, Krishna C. Saraswat, “Band to Band Tunneling Study in High Mobility Materials : III-V, Si, Ge and strained SiGe”, Device Research Conference, 2007 65th Annual, pp.57-58.
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