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研究生:柯仲修
研究生(外文):Tsung-Hisu Ko
論文名稱:規則架構電路之內建自我測試技術
論文名稱(外文):Built-In Self-Test for Regularly Structured Circuits
指導教授:黃俊郎黃俊郎引用關係
指導教授(外文):Jiun-Lang Huang
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電機工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:96
語文別:英文
論文頁數:50
中文關鍵詞:自我測試規則架構自我重新裝配容錯
外文關鍵詞:self-testingregular structurereconfigurationfault tolerance
相關次數:
  • 被引用被引用:0
  • 點閱點閱:170
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測試一直是IC產業中不可或缺的一環,如何讓測試變的更有效率,一直是一個重要的議題。當IC元件持續地變小,隨之而來的是IC整體的複雜度大大地提升,這使得測試的難度也變得更高。可靠度是另外一個IC產業中相當重要的議題,尤其是對於某些應用的IC,像是醫療器材或是操控飛機的元件。
在這篇論文裡,我們對於規則架構的電路提出(1)一個可以運用在在線測試的內建自我測試技術(2)一個自我重新裝配的方法來使電路的可靠度提高。在在線測試的過程中,錯誤的區塊將會被找出來,接著電路將會自我重新裝配來保持正確的功能。相較於之前的方法,我們所提出的方法有下列優點: (1)因為我們的使用決定性的內建自我測試電路,所以目標錯誤的偵測是保證的。(2)由於內建自我測試電路利用了原本電路的規則性,輸出響應並不需要額外的儲存起來,這可以減少內建自我測試電路的面積。本技術的限制在於當在線測試的過程中或是自我重新裝測後,效能將會減低。
目前我們所提出的技術適用於由重複的單向元件所組成的規則架構電路,我們把此技術運用在兩個常用的電路來證明他的有效性,分別是前視進位加法器(Carry Look-Ahead Adder)和用在MPEG的處理元件(Processing Element)陣列。前視進位加法器被修改成有自我檢測和自我重新裝配的能力,且內建自我測試電路可以達到幾乎100%的錯誤涵蓋率。至於處理元件陣列和之後的最小值樹,我們設計了一個高錯誤涵蓋率的測試圖樣產生器。
誌謝 I
中文摘要 II
Abstract III
Table of Contents IV
List of Figures V
List of Tables VI
Chapter 1 Introduction 1
Chapter 2 Preliminaries 3
2.1 Fault tolerance and self-checking 3
2.2 Built-in self-test (BIST) 6
2.3 C-testable and linear-testable 7
Chapter 3 Proposed on-line testing and reconfiguration technique 9
3.1 On-line testing 9
3.2 Reconfiguration technique 11
Chapter 4 BIST for the carry look-ahead adder 13
4.1 Introduction of adders 13
4.2 Proposed self-testing and self-reconfiguration CLA 17
4.3 Test pattern generator 24
4.3.1 Pattern for SSF 24
4.3.2 Pattern for transition fault 25
Chapter 5 BIST for motion estimation 27
5.1 Background for video coding 27
5.2 Motion estimation 28
5.3 BIST for PE array 31
5.4 BIST for minimum tree 36
Chapter 6 Experimental result 43
6.1 Result of the design on CLA 43
6.2 Result of the design on PE array and minimum tree 45
Chapter 7 Conclusions 48
References 49
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[10]M. Nicolaidis, “Carry Check/Parity Prediction Adders and ALUs,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Feb. 2003, vol. 11, pp. 121-128.
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[14]P. Oikonomakos, P. Fox, “Error Correction in Arithmetic Operations by I/O Inversion,” in Proc. International On-Line Testing Symposium, 2006.
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[17]S-K Lu, J-C Wang, C-W Wu, “C-Testable Design Techniques for Iterative Logic Arrays,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Mar. 1995, vol. 3, pp. 146-152.
[18]V. Bhaskaran, K. Konstantinides, “Image and Video Compression Standards 2nd Edition,” Kluwer Academic Publishers, pp. 100-122.
[19]B. Johnson, J. Aylor, H. Hana, “Efficient Use of Time and Hardware Redundancy for Concurrent Error Detection,” IEEE Journal of Solid-State Circuits, Feb. 1988, vol. 23, pp. 208-215.
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