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研究生:洪麗玲
研究生(外文):Li-ling Hung
論文名稱:在多重電腦模式及電路模式的有效率平行前置演算法
論文名稱(外文):Efficient Parallel Prefix Algorithms on the Multicomputer and Circuit Models
指導教授:林彥君林彥君引用關係
指導教授(外文):Y.-C. LIN
學位類別:博士
校院名稱:國立臺灣科技大學
系所名稱:資訊工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:96
語文別:英文
論文頁數:92
中文關鍵詞:組合電路計算有效率的平行前置演算法成本最佳深度及節點數最佳訊息傳遞的多重電腦平行演算法前置問題與問題大小無關腰部及節點數最佳
外文關鍵詞:combinational circuitcomputation-efficient parallel prefixcost optimalitydepth-size optimalmessage-passing multicomputerparallel algorithmsprefix problemproblem-size-independentwaist-size optimal
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前置運算是對n個輸入x1, x2,…, xn進行具結合性的二元運算♁計算求得n個前置值x1 ♁ x2 ♁…♁ xi, 1 ≤ i ≤ n。前置運算已被廣泛應用在很多領域,且被視為一種基本運算。本論文分別在多重電腦(multicomputer)模式及組合電路(combinational circuit)模式提出有效率的平行前置演算法。多重電腦使用分散式記憶體(distributed memory)架構,利用訊息傳遞(message passing)進行資料的交換,其執行時間包含計算時間及通訊時間。我們提出四群計算有效率的演算法。前兩群演算法乃改善既有之演算法,減少其執行時間;另外兩群則使用更強的通訊模式,分別縮短前兩群演算法的通訊時間。在論文中也提出可有效使用此四群演算法應有的先決條件。這些演算法提供使用者彈性,可視軟硬體設備等級來選擇適當演算法以達到最短的執行時間。
前置電路是組合電路的前置演算法。對任一寬度(即輸入埠個數)為m的前置電路A,其深度d(A)與運算節點數s(A)有d(A) + s(A) ≥ 2m – 2的關係。因此,若d(A) + s(A) = 2m – 2則稱A為深度及節點數最佳電路。較小的深度代表執行時間較快,運算節點數少代表所需的成本及消耗功率低。若前置電路A的腰部(waist)為w(A),則有w(A) + s(A) ≥ 2m – 2的關係。若w(A) + s(A) = 2m – 2且w(A) = 1,則稱A為WSO-1電路。另外,節點的扇出(fan-out)等於節點的出度(out degree),前置電路的扇出為電路中所有節點的最大扇出。由於節點的扇出愈大,除了功率損耗愈大外,所需要的積體電路面積愈大,也會使輸出的速度變慢。因此,實用上,前置電路的扇出要愈小愈好。本論文所提出的前置電路扇出均為2。
本論文提出一群WSO-1平行前置電路,這群電路不但可以組成深度小的深度及節點數最佳電路,也是在輸入資料個數大於電路寬度時較快的電路。這群電路與其他的電路比較,當輸入個數比電路寬度大越多時,速度越快。而且,當輸入資料個數大於或等於電路寬度2倍時,這群新電路比所有電路都要快。本論文也建構一群深度及節點數最佳電路;與另外兩群深度及節點數最佳電路的建造方法相較,我們建造新電路的方法是最直接且最適合自動化。電路結構平衡也是新電路的一個優勢。
Given n inputs x1, x2,…, xn and an associative binary operator ♁, the prefix problem, or prefix computation, is to compute yi = x1 ♁ x2 ♁…♁ xi, for 1 ≤ i ≤ n. Prefix computation is used in various areas and is considered as a primitive operation. This thesis presents efficient algorithms for both multicomputer and combinational circuit models. Four families of computation-efficient parallel prefix algorithms for the multicomputer are given. The first two families generalize previous algorithms that use only half-duplex communications, and can improve the running time. The third and fourth families adopt collective communication operations to improve the communication time of the first two, respectively. The precondition of all the presented algorithms is also derived. The families of algorithms each provide the flexibility of choosing either less computation time or less communication time to achieve the minimal running time depending on the ratio of the time required by a communication step to the time required by a computation step.
Parallel prefix circuits are parallel prefix algorithms on the combinational circuit model. The depth of a prefix circuit A, d(A), is a measure of its processing time; smaller depth implies faster computation. The size of a prefix circuit A, s(A), is the number of operation nodes in it; smaller size implies less power consumption, less VLSI area, and less cost. For any prefix circuit A of width m, which is the number of inputs, it has been shown that d(A) + s(A) ≥ 2m – 2; thus, A is depth-size optimal if d(A) + s(A) = 2m – 2. With the definition w(A), which is called waist of A, for any prefix circuit A of width m, it has been known that s(A) + w(A) ≥ 2m – 2. If s(A) + w(A) = 2m – 2 and w(A) = 1, then A is said to be waist-size optimal with waist 1 (WSO-1). A circuit with a smaller fan-out is in general faster and occupies less VLSI area. To be of practical use, the depth and fan-out of a prefix circuit should be small. This thesis presents prefix circuits with the smallest fan-out 2.
In this thesis, a family of parallel prefix circuits is presented. These prefix circuits are WSO-1. They are not only building blocks for constructing fast depth-size optimal prefix circuits, but also themselves fast problem-size-independent prefix circuits. When the problem size is greater than the circuit width, a new prefix circuit may be well faster than any other prefix circuits of the same width, especially when the problem size is greater than or equal to twice the circuit width. The new prefix circuits are compared analytically with other representative ones circuits to show how fast they are. They have the minimum depth and are the fastest among all WSO-1 prefix circuits of the same width and fan-out. They are also better building blocks than other circuits for constructing fast depth-size optimal prefix circuits. A family of depth-size optimal, parallel prefix circuits with fan-out 2 is also presented. It is easier to construct and more amenable to automatic synthesis than two other families, all sharing the same minimum depth. The balanced structure of the new family is also a merit.
摘要 i
Abstract iii
1. Introduction 1
1.1. Prefix computation 1
1.1.1. Multicomputer model 2
1.1.2. Prefix circuit model 3
1.2. Related work 5
1.2.1. Multicomputer algorithms 5
1.2.2. Prefix circuits 5
1.3. Contributions 8
1.4. Overview 8
2. Previous prefix algorithms on the multicomputer 10
3. Four new families of parallel prefix algorithms 12
3.1. Algorithm A 12
3.2. Algorithm B 16
3.3. Algorithms E and F 17
4. Analysis of new algorithms 18
4.1. Computation time of the algorithms 18
4.2. Communication time of Algorithm A 21
4.3. Communication time of Algorithm B 24
4.4. Communication time of Algorithms E and F 27
4.5. Precondition of algorithms 29
5. Comparisons of related algorithms 32
6. Previous results on prefix circuits 38
7. New parallel prefix circuits with fan-out 2 44
7.1. H: a family of waist-size optimal prefix circuits 44
7.2. HI and HD: Two families of waist-size optimal prefix circuits 51
7.3. C2: A family of depth-size optimal prefix circuits 52
8. Comparisons of prefix circuits 57
8.1. Problem-size-independent prefix circuits 57
8.2. Depth-size optimal prefix circuits 62
9. Conclusions and future work 64
Appendix A. Lemma A.1 66
Appendix B. Proof of Theorem 1 67
References 71
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