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研究生:張珈瑋
研究生(外文):Chia-wei Chang
論文名稱:整合24GHz壓控振盪器與8GHz注入鎖定除頻器之設計
論文名稱(外文):Design of Integrated 24GHz Voltage Controlled Oscillator and 8GHz Injection Locked Frequency Divider
指導教授:黃進芳黃進芳引用關係張勝良
指導教授(外文):Jhin-Fang HuangSheng-Lyang Jang
學位類別:碩士
校院名稱:國立臺灣科技大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:96
語文別:英文
論文頁數:111
中文關鍵詞:電壓控制振盪器注入鎖定除頻器3D電感
外文關鍵詞:VCOILFD3D Inductor
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壓控振盪器與除頻器是頻率合成器電路中,主要的電路之一。對壓控振盪器而言,低相位雜訊可避免相鄰雜訊訊號經由混波轉換的干擾。而振盪器的輸出則經由除頻器來達成降頻的工作,因此,除頻器需具有高頻操作、寬的操作頻寬及低功率消耗。
本論文將描述如何設計金氧半壓控振盪器與直接注入鎖定除頻器,第一部分我們提出了一個寬鎖頻範圍的3D電感直接注入除3電路,此電路使用台積電所提供之零點一八微米互補式金氧半製程所製造,此除頻器使用一組nMOS交錯耦合的LC振盪器加上兩個串聯注入的MOSFETs,其中LC共振器電感為自製的3D電感,達到了減小面積及增加鎖頻範圍之功效。
第二部分我們提出了一個整合壓控振盪器與除頻器的電路,除頻器為一個使用並聯式注入的8GHz直接注入鎖定除三電路,再搭配一個24GHz的壓控振盪器整合於同一晶片,此電路使用台積電所提供之零點一八微米互補式金氧半製程所製造,除頻器可以鎖定除頻壓控振盪器的輸出訊號,並且鎖定除頻後比未鎖定除頻前有更低的相位雜訊。
The key building blocks in the frequency synthesizer are the voltage controlled oscillator (VCO) and the high frequency divider circuit. Most importantly, low phase-noise is required to avoid corrupting the mixer-converted signal by close interfering tones for VCO circuit. The output of the VCO is divided down by the frequency divider which requires operating at high frequencies, wide operating range and lower power consumption.
This thesis studies the design of CMOS Voltage-Controlled Oscillator and injection-locked frequency divider. The first part proposes a wide-locking range divide-by-3 frequency divider employing 3D helical inductors fabricated in the 0.18-μm 1P6M CMOS technology. The divider consists of an nMOS cross-coupled LC oscillator and two injection MOSFETs in series with the cross-coupled NMOSFETs, and the LC resonator is composed of two 3D helical inductors and varactors. The aim of using 3D inductor is to reduce chip size.
The second part of this thesis proposes an integrated VCO-divider circuit, the divide-by-3 injection locked frequency divider consists of a 8GHz nMOS-core VCO with two parallel injection MOSFETs and the VCO is a 24GHz double cross-coupled np-core CMOS VCO. The circuit is implemented in a standard 0.18-μm CMOS process. The ILFD can lock to the VCO and outputs a lower phase noise source than the free running ILFD.
Contents
中文摘要 1
ABSTRACT 3
誌謝 4
CONTENTS 5
LIST OF FIGURES 7
LIST OF TABLES 10
CHAPTER 1 INTRODUCTION 11
1.1 BACKGROUND 11
1.2 THESIS ORGANIZATION 14
CHAPTER 2 OVERVIEWS OF VOLTAGE-CONTROLLED OSCILLATORS AND INJECTION-LOCKED FREQUENCY DIVIDER 15
2.1 THE OSCILLATOR 15
2.1.1 Negative Resistance (NR) 15
2.1.2 Positive Feedback (PFB) 18
2.2 ALL TYPES OF OSCILLATORS 20
2.2.1 Ring Oscillator 21
2.2.2 LC-Tank Oscillator 24
2.3 VOLTAGE-CONTROLLED OSCILLATOR 28
2.4 THE PARAMETERS OF VCOS 29
2.4.1 Center Frequency 29
2.4.2 Tuning Range 29
2.4.3 Tuning Linearity 30
2.4.4 Output Amplitude 31
2.4.5 Power Dissipation 31
2.4.6 Supply and Common-Mode Rejection 32
2.4.7 Output Signal Purity 32
2.5 PHASE NOISE 32
2.5.1 Definition of Phase Noise 33
2.5.2 Existing Models of Phase Noise 35
2.5.2.1 Time-invariant phase noise model 35
2.5.3 Noise Sources 37
2.5.4 Phase Noise in Wireless Communication 42
2.5.5 Previous Models of Phase Noise 44
2.6 ON-CHIP INDUCTOR RESEARCH 46
2.7 VARACTOR 56
2.7.1 P-N Junction Varactor 56
2.7.2 MOS Varactor 57
2.8 RESISTORS 63
2.9 INJECTION LOCKING 64
CHAPTER 3 DIVIDE-BY-3 LC INJECTION LOCKED FREQUENCY DIVIDER IMPLEMENTED WITH 3D INDUCTORS 70
3-1. INTRODUCTION 70
3-2. CIRCUIT DESIGN 72
3-3. MEASUREMENT RESULTS 82
3-4. CONCLUSION 91
CHAPTER 4 INTEGRATED 24GHZ LC VCO AND 8GHZ DIVIDE-BY-3 FREQUENCY DIVIDER 92
4-1. INTRODUCTION 92
4-2. DESIGN OF VCO AND ILFD CIRCUITS 94
4-3. MEASUREMENT RESULTS 100
4-4. CONCLUSION 105
CHAPTER 5 CONCLUSION 106
REFERENCES 108
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